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The Trenz Electronic TE0823 (3PIU1FA /3PIU1FL)  is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CGMPSoC, 1 GByte LPDDR4 SDRAM, 128 MByte Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

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All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • SoC/FPGA
    • Package: SFVC784, SFRC784
    • Device: ZU2 ...ZU5, *
    • Engine:  EG, CG, EV, *
    • Speed: -1, -1L, -2, -2L, 3, *, **
    • Temperature: I, E, *, **
  • RAM/Storage
    • 2x  DDR4 SDRAM,
      • Data Width: 32 Bit
      • Size: 16 Gb, *
      • Speed: 3733 Mbps, ***
    • 2x QSPI boot Flash in dual parallel mode
      • Data Width: 8 Bit
      • Size: 512 Mb Gb, *
    • 1x e.MMC Memory
      • Data Width: 8 Bit
      • Size: 32 Gb, *
    • MAC address serial EEPROM
  • On Board
    • Lattice MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 4x LEDS
  • Interface
    • 1x GB/s serial GMII interface
    • 1x Hi-speed USB2 ULPI transceiver with full OTG support
    • 154 x High Performance (HP) und 96 x High Density (HD) I/Os
    • 78 x PS MIOs
    • 4 x serial PS GTR transceivers
      • PCI Express interface version 2.1 compliant
      • SATA 3.1 specification compliant interface
      • DisplayPort source-only interface with video resolution up to 4k x 2k

      • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • Power
    • All power regulators on board
  • Dimension
    • 40 x 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration
  • Block Diagram

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Signal

B2BI/ONote

ENRESIN

JM1JM2-2818InputCPLD Enable Pin


Signals, Interfaces and Pins

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The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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MIO
PinSchematicU?? PinNotes
QSPI, U7QSPI, U17Notes
nCSMIO5MIO7
CLKMIO0MIO12
DI/IO0MIO4MIO8
DO/IO1MIO1MIO9
nHOLD/IO3MIO3MIO11
WP/IO2MIO2MIO10


EEPROM

There is a 2Kb EEPROM provided on the module TE0821.

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MIO PinSchematicU?? PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL



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MIO PinI2C AddressDesignatorNotes
MIO38-MIO390x50U25


LEDs

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DesignatorColorConnected toActive LevelNote
D1RedDONELow
D2GreenUSR_LEDHigh
D3RedERR_OUTHigh
D4GreenERR_STATUSHigh


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