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Xilinx Spartan-3 generation FPGAs have a dedicated four-wire IEEE 1149.1/1532 JTAG port that is always available any time the FPGA is powered and regardless of the mode pin settings. However, when the FPGA mode pins are set for JTAG mode (M[2:0] = <1:0:1>), the FPGA waits to be configured via the JTAG port after a power-on event or after PROG_B is pulsed Low. Selecting the JTAG mode simply disables the other configuration modes. No other pins are required as part of the configuration interface.
M0-M2 have Pull ups in FPGA.
If S1B S1C is off, then signals from B2B should be left float. If S1B C1C is on, then mode can be set from B2B.
Stop condition: Never set Mx from B2B directly to one,
The table below shows some options about setting mode pin M2 high or low.

The table below Table 21: mode pin M2 settings.
Table 22 shows some options about setting mode pin M1 high or low.

Table 22: mode pin M1 settings.
Table 23 The table below shows some options about setting mode pin M0 high or low.

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 Table 23: mode pin M0 settings.

Figure 44: configuration modes schematic