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The mode select pins M[2:0] define the configuration mode that the FPGA uses to load its bitstream. The table below shows the configuration modes supported by TE0320. The logic level applied to the mode pins is sampled on the rising edge of INIT_B, immediately after the FPGA completes initializing its internal configuration memory. See Xilinx UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals.

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The table below shows some options about setting mode pin M1 high or low.

The table below shows some options about setting mode pin M0 high or low.

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Figure 44: configuration modes schematic