This section describes how to configure the TE USB FX2 module and access some of its resources.
TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller to provide a high-speed USB 2.0 interface. The controller uses 4 interfaces (see here):
The I2C interface connects the USB controller to the EEPROM chip, which stores vendor ID and device ID. See chapter DIP Switch for available options.
The SPI interface id used to communicate with the FPGA and to access the SPI serial Flash chip.
The FIFO interface provides a high-speed communication channel with the FPGA. The interface can transfer up to 48 MB/s burst rate.To program the firmware in the EEPROM, the IIC bus should be correctly configured.
To program the bitstream in the Flash, the SPI bus should be correctly configured.
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The JTAG interface allows a fast, frequent but volatile configuration (only the FPGA is programmed and not the SPI Flash) of the TE USB FX2 module. However, only through the JTAG interface it is possible to develop and debug with Xilinx tools (e.g. Xilinx ChipScope, Xilinx Microprocessor Debugger. The JTAG interface allows also a occasional, non-volatile on-site operations such as SPI Flash bitstream download.
Configuration of the TE USB FX2 module through a USB host is recommended for occasional, non-volatile on-site operations such as firmware upgrade or SPI Flash bitstream download.
TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller to provide a high-speed USB 2.0 interface. The controller uses 4 interfaces (see here):