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Configuration mode connections available to the user

Scroll pdf title
titleConfiguration modes overview: FPGA bitstream only.
TE USB FX2 module typeConfiguration mode connections
TE0630TE0300Image Modified
TE0320
TE0300TE0630Image Modified

USB interface

TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller (TE USB FX2 microcontroller) to provide a high-speed USB 2.0 interface. Configuration of the TE USB FX2 module through a USB host is recommended for non-volatile on-site operations such as firmware upgrade or SPI Flash bitstream download.

Even when USB connector is used to program the FPGA image (aka FPGA bitstream), the SPI bus and the the SPI Flash memory are also used by C#  OpenFutNet or Python Open_FUT.

Info

 The procedure followed by one of the two TE programs (or by a custom user program) is the following:

  • erase the SPI Flash (FLASH_ERASE command);
  • writes the bitstream image in the SPI Flash (FLASH_WRITE command) and readback the bytes written (FLASH_READ command) for integrity check; 
  • after SPI Flash writing is complete and checked, the FPGA is powered off (POWER command with command[1]=0) and then on (POWER command with command[1]=1);
  • at power on the FPGA automatically read the SPI Flash content to configure itself;
  • waits some seconds (2 to 10 seconds) the end of  FPGA configuartion;the FX2 microcontroller's firwmare is able to read the DONE PIN status from PD2 pin (IOD2)
  • a READ_STATUS command should be used to check if DONE PIN (reply[4] = EP1INBUF[4] = sts_booting) is high (reply[4]=1) .

Even when USB connector is used to program the FX2 microcontroller's firmware, the IIC bus and the the IIC EEPROM memory are also used by C#  OpenFutNet or Python Open_FUT.

Jtag Interface

The JTAG interface allows a

  • fast (10 seconds), frequent but volatile configuration (only the FPGA is programmed using Xilinx ISE or EDK and a .bit bitstream and not the SPI Flash) of the TE USB FX2 module.
  • medium-fast (1-2 minutes) non-volatile on-site operations such as SPI Flash bitstream download: indirect SPI in-system programming (ISP).
Info
Only through the JTAG interface it is possible to develop and debug with Xilinx tools (e.g. Xilinx SDK debug,Xilinx ChipScope, Xilinx Microprocessor Debugger).

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When the FPGA mode pins are set for JTAG mode (M[2:0] = <1:0:1> in TE0320 and TE0300 module), the FPGA waits to be configured via the JTAG port after a power-on event or after PROG_B is pulsed Low. Selecting the JTAG mode simply disables the other configuration modes. No otherpins other pins are required as part of the configuration interface.

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