Page History
...
Scroll pdf ignore | ||||
---|---|---|---|---|
Table of contents
|
Overview
Firmware for PCB RFSoC module CPLD with designator U31. Second CPLD Device in Chain: LCMX02-640HC
Feature Summary
- Firmware
- Power Management
- JTAG routing
- LED
...
Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
---|---|---|---|---|
MIO13PWR_STATUS | out | 36 | 1.8V_CPLD | Output to drive gate of MOSFET transistor for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0) |
MODE0 | out | 35 | 1.8V_CPLD | ZynqMP boot mode pin 0 |
PG_VCCRF | in | 34 | 1.8V_CPLD | Power Good input from PWR_PRE |
SRST_B | out | 33 | 1.8V_CPLD | FPGA external system reset / currently_not_used |
PROG_B | out | 32 | 1.8V_CPLD | FPGA reset PL configuration logic / currently_not_used |
PG_GR2 | in | 31 | 1.8V_CPLD | Power control input from PWR_PS and PWR_DDR |
MIO28_UART1_TX | out | 29 | 1.8V_CPLD | UART Transmition pin / currently_not_used |
MIO28_UART1_RX | in | 28 | 1.8V_CPLD | UART Receive pin / currently_not_used |
FPGA_IO0 | inoutout | 27 | 1.8V_CPLD | FPGA GPIO / currently_not_usedGPIO / User LED |
FPGA_IO1 | inoutin | 26 | 1.8V_CPLD | FPGA GPIO / currently_not_usedUser dip switch interface |
EN_PS_PL | out | 14 | 3.3V_CPLD | Power enable for PWR_CORE , PWR_PS and PWR_GT |
EN_GR1 | out | 15 | 3.3V_CPLD | Power enable for PWR_GT and PWR_PS |
EN_RF_ADC | out | 16 | 3.3V_CPLD | Power enable for PWR_ADC |
PG_RF_DAC | in | 17 | 3.3V_CPLD | Power control input from PWR_DAC |
EN_VCCRF | out | 18 | 3.3V_CPLD | Power enable for PWR_PRE |
EN_GR2 | out | 19 | 3.3V_CPLD | Power enable for PWR_DDR , PWR_GT and PWR_PS |
PG_PS_PL | in | 20 | 3.3V_CPLD | power control input from PWR_CORE , PWR_GT and PWR_PS |
PG_GR1 | in | 21 | 3.3V_CPLD | Power control input from PWR_GT and PWR_PS |
PG_RF_ADC | in | 23 | 3.3V_CPLD | Power control input from PWR_ADC |
EN_RF_DAC | out | 24 | 3.3V_CPLD | Power enable for PWR_DAC |
MODE2 | out | 2 | 1.8V_CPLD | ZynqMP boot mode pin 2 |
MODE1 | out | 3 | 1.8V_CPLD | ZynqMP boot mode pin 1 |
POR_B | out | 4 | 1.8V_CPLD | Power-On reset signal |
MODE3 | out | 5 | 1.8V_CPLD | ZynqMP boot mode pin 3 |
INIT_B | in | 7 | 1.8V_CPLD | FPGA PL initialization activity and configuration error signal / currently_not_used |
F_TDI | out | 8 | 1.8V_CPLD | JTAG ZynqMP |
F_TMS | out | 9 | 1.8V_CPLD | JTAG ZynqMP |
F_TCK | out | 10 | 1.8V_CPLD | JTAG ZynqMP |
F_TDO | in | 11 | 1.8V_CPLD | JTAG ZynqMP |
DONE | in | 12 | 1.8V_CPLD | FPGA PL configuration done indicator / currently_not_used |
JTAG_TDO | out | 48 | 3.3V_CPLD | JTAG_B2B |
JTAG_TDI | in | 47 | 3.3V_CPLD | JTAG_B2B |
JTAG_TCK | in | 45 | 3.3V_CPLD | JTAG_B2B |
JTAG_TMS | in | 44 | 3.3V_CPLD | JTAG_B2B |
CPLD_IO0 | in | 43 | 3.3V_CPLD | BOOT Mode input pin 0 |
CPLD_IO1 | in | 42 | 3.3V_CPLD | BOOT Mode input pin 1 |
CPLD_JTAGEN | in | 41 | 3.3V_CPLD | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
CPLD_IO2 | inout | 40 | 3.3V_CPLD | CPLD IO / currently_not_usedto B2B / Used as dip switch interface on the carrier board (After successful configuration of FPGA is connected automatically with FPGA_IO1) |
CPLD_IO3 | inout | 38 | 3.3V_CPLD | CPLD IO / currently_not_usedto B2B/ Used as power good, can be used to enable carrier periphery power |
RESETN | in | 37 | 3.3V_CPLD | Reset pin of CPLD (Active low) |
Firmware
See Document Change History.
Functional Description
JTAG
...
According to the Xilinx instructions the power regulator or DC-DC converter must be switched on or off in a certain order. This is called power-on or power-off sequencing.To implement power-on sequencing correctly, a state machine must be running there. In the following you can see the State Machine Diagram.
LED
draw.io Diagram | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Stage | Control | Voltage Domains | Signal Monitoring to change stage |
---|---|---|---|
IDLE | --- | --- | --- |
STAGE0 | EN_PS_PL enabled (High) | 0.853V, 0.85V, 0.9V | --- |
STAGE1 | EN_GR1 enabled (High) | 1.8V, 0.85V, 1.2V | PG_PS_PL |
STAGE2 | EN_GR2 enabled (High) | 3.3V, 1.8V | PG_GR1 |
STAGE3 | EN_VCCRF enabled (High) | 0.8534V, 1.158V, 3.3V | PG_GR2 |
STAGE4 | EN_RF_ADC enabled (High) EN_RF_DAC enabled (High) | 0.925V, 1.8V 0.925V, 1.8V, 2.5V | PG_VCCRF |
STAGE5 | --- | --- | PG_RF_ADC PG_RF_DAC |
WAIT_RDY | --- | --- | pg_all |
RDY | por enabled (High) | --- | pg_all |
- pg_all <= PG_PS_PL & PG_GR1 & PG_GR2 & PG_VCCRF & PG_RF_ADC & PG_RF_DAC
- If por is high then POR_B (power-on reset signal) will be deactivated.
LED
StatesPower Stage | Blink Sequence | Comment | ||||
---|---|---|---|---|---|---|
IDLE | ***************oooooooooooooooooooo* | Power Sequencing can not start. RESETN is active. | ||||
Stage 0 | ooooooooooooooooo*o* | First enable signal (EN_PS_PL) is activated. | ||||
Stage 1 | ooooooooooooooo*o*o* | The correct voltage in one ***********o*oOne of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC | ||||
Stage | 12 | **********ooooooooooooo*o*o*o* | oThe correct voltage in one of | One ofthe following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT | ||
Stage 23 | ooooooooooo*o********o*o*o*o | The correct voltage in one of One of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2 | ||||
Stage 34 | ooooooooo*o******o*o*o*o*o | The correct voltage in one of One of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3 | ||||
Stage 45 | ooooooo***o**o*o*o*o*o*o | The correct voltage in one of One of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT | ||||
WAIT_RDY | ooooo*o*o*o*o*o*o*o* | All power good signals are checked again. | ||||
RDY | OFF | Power is ok. | ||||
ERROR | o*o*o*o*o*o*o*o*o | One of the last stages is not ok | RDY | oooooooooooooooo | Power is ok*o* | The main power supply must be switched off. |
USR | User defined | LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high) |
- The period for erery blink (*o) is 0.5sec.
Boot Mode
Boot Modes can be selected via B2B Pin Mode.
...
Appx. A: Change History and Legal Notices
Revision Changes
- REV00 REV01 to REV01REV02
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
...
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV02, REV01 |
|
| ||||||||||||||||||||||
2020-08-18 | v.4 | REV00 | REV01 | Ivan Girshchenko / Mohsen Chamanbaz |
| ||||||||||||||||||||||
All |
|
...