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Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TEM0005-02 is a low-cost, small FPGA module with Microsemi SmartFusion2 FPGA SoC and 32 MByte flash memory for configuration and operation. SmartFusion2 combines a 166 MHz Cortex-M3 MCU with 256 KByte Flash and 80 KByte SRAM as well as 12 kLUT FPGA Core Logic.
Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.
Key Features
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGA
- Package: VFG400
- Device: M2S005, M2S010, M2S025,M2S050,M2S060*
- Engine: VFG
- Speed: -1, Standard*, **
- Temperature: C, I,*, **
- RAM/Storage
- Low Power DDR3
- Data width: 8/16bit
- Size: def. 2Gb*
- Speed: 20ns***
- QSPI
- Data width: 8 bit
- size: 256 M bit *
- 2Kb EEPROM
- On Board
- Crypto Authentication IC
- Voltage monitor IC
- 10/100 Mbps PHY Ethernet
- Interface
- Power
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used FPGA and DDR3 combination
Block Diagram
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title | TEM0005 block diagram |
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Main Components
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- Microsemi SmartFusion, U2
- Reg, U7
- EEPROM, U4
- 10/100 Mb Ethernet, U1
- QSPI Flash, U3
- Authentication IC, U6
- DDR3 Memory, U5
- B2B Connector, J1
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| EEPROM | Not Programmed |
| DDR3 SDRAM | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Signal | B2B | I/O | Note |
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RESET
| J1-11 |
| Active low reset |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the TEM0005 SoM through B2B connector J1.
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title | JTAG pins connection |
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JTAG Signal | B2B Connector |
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TMS | J1-14 | TDI | J1-8 | TDO | J1-10 | TCK | J1-12 | JTAG_EN | J1-7 |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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title | Test Points Information |
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Test Point | Signal | Connected to | Notes |
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TP1 | CLKOUT | Regulator, U7 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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title | On board peripherals |
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Chip/Interface | Designator | Notes |
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QSPI | U3 |
| DDR3 SDRAM | U5 |
| EEPROM | U4 |
| Authentication IC | U6 |
| Ethernet | U1 |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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MIO Pin | Schematic | U?? Pin | Notes |
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EEPROM
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title | I2C EEPROM interface MIOs and pins |
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MIO Pin | Schematic | U?? Pin | Notes |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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MIO Pin | I2C Address | Designator | Notes |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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U?? Pin | Signal Name | Connected to | Signal Description | Note |
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Clock Sources
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anchor | Table_OBP_CLK |
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title | Osillators |
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orientation | portrait |
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Designator | Description | Frequency | Note |
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Y3 | Crystal Oscillator | 25 MHz |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 1.5 A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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diagramName | TEM0005_PWR_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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diagramWidth | 641 |
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revision | 3 |
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Power-On Sequence
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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diagramName | TEM0005_PWR_PS |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Power Rails
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anchor | Table_PWR_PR |
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title | Module power rails. |
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Power Rail Name | B2B Connector JM1 Pin | Direction | Notes |
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3.3V | 1, 2, 3, 4 | Output |
| VDDI6 | 22 | Input |
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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| Schematic Name | | Notes |
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Bank0 | VDDI0 | 1.5V |
| Bank1 | VDDI1 | 3.3V |
| Bank2 | VDDI2 | 3.3V |
| Bank3 | VDDI3 | 3.3V |
| Bank4 | VDDI4 | 3.3V |
| Bank5 | VDDI6 | 3.3V |
| Bank6 | VDDI6 | 3.3V |
| Bank7 | VDDI7 | 3.3V |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
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| 3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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VIN | Input Supply Voltage |
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| V | STG_T | Storage Temperature |
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| °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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title | Recommended operating conditions. |
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orientation | portrait |
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Parameter | Min | Max | Units | Reference Document |
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VIN |
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| V | See the carrier datasheets. | OPT_T |
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| °C | See Microsemi Smartfusion2 ???? datasheet. |
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Physical Dimensions
PCB thickness: 1.6 mm.
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title | Physical Dimension |
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diagramName | TEM0005_TS_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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Date | Revision | Changes | Documentation Link |
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| REV01 | Initial Release | REV01 |
| REV02 | - Support M2S050 -> added R29,R30, C24..C26,C31
- Added resistor R32
- Full upd LIB
| REV02 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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title | Board hardware revision number. |
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width | 200 |
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revision | 6 |
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Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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title | Document change history. |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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Page properties |
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|
Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
|
HTML |
---|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
Page properties |
---|
|
Important General Note:
|
Page properties |
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----------------------------------------------------------------------- |
Page properties |
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|
Note for Download Link of the Scroll ignore macro: |
Scroll pdf ignore |
---|
Table of Contents |
Overview
The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...
Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.
Key Features
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- <Replace for module use "SoC/FPGA" for Carrier "Modules">
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Notes
Block Diagram
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add drawIO object here.
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anchor | Figure_OV_BD |
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title | TEM0005 block diagram |
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draw.io Diagram |
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border | false |
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diagramName | TEM0005_OV_BD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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revision | 9 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Scroll Title |
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anchor | Figure_OV_MC |
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title | TEM0005 main components |
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draw.io Diagram |
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border | false |
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diagramName | TEM0005_OV_MC |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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revision | 20 |
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- ...
- ...
- ...
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Scroll Title |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash |
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| EEPROM |
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| System Controller CPLD |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_BP |
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title | Boot process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MODE Signal State | Boot Mode |
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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JTAG Signal | B2B Connector |
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TMS |
| TDI |
| TDO |
| TCK |
| JTAG_EN |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOs |
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title | MIOs pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Connected to | B2B | Notes |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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Scroll Title |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Connected to | Notes |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U?? Pin | Notes |
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RTC
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U? Pin | Notes |
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Scroll Title |
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anchor | Table_OBP_I2C_RTC |
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title | I2C Address for RTC |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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EEPROM
Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U?? Pin | Notes |
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Scroll Title |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
Scroll Title |
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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U?? Pin | Signal Name | Connected to | Signal Description | Note |
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CAN Transceiver
Scroll Title |
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anchor | Table_OBP_CAN |
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title | CAN Tranciever interface MIOs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank | Schematic | U?? Pin | Notes |
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| D-Tx |
| Driver Input |
| R-Rx |
| Reciever Output |
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Clock Sources
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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Y3 | Crystal Oscillator | 25 MHz |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
Scroll Title |
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anchor | Table_OBP_PCLK |
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title | Programmable Clock Generator Inputs and Outputs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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U?? Pin
| Signal | Connected to | Direction | Note |
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IN0 |
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| IN1 |
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| IN2 |
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| IN3 |
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| XAXB |
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| SCLK |
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| SDA |
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| OUT0 |
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| OUT1 |
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| OUT2 |
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| OUT3 |
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| OUT4 |
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| OUT5 |
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| OUT6 |
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| OUT7 |
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| OUT8/OUT9 |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TEM0005_PWR_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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Scroll Only |
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Power-On Sequence
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TEM0005_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 1 |
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Scroll Only |
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Voltage Monitor Circuit
Scroll Title |
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 Pin | Direction | Notes |
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3.3V | 1, 2, 3, 4 | Output |
| VDDI6 | 22 | Input |
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Bank Voltages
Scroll Title |
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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Bank0 | VDDI0 | 1.5V |
| Bank1 | VDDI1 | 3.3V |
| Bank2 | VDDI2 |
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| Bank3 | VDDI3 |
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| Bank4 | VDDI4 |
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| Bank5 | VDDI6 |
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| Bank6 | VDDI6 |
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| Bank7 | VDDI7 |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
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| 3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
Scroll Title |
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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VIN | Input Supply Voltage | -5 | 5 | V | T_STG | Storage Temperature | -55 | 155 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Scroll Title |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN |
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| V | See the carrier datasheets. | T_OPT | -45 | 125 | °C | See Microsemi Smartfusion2 datasheet. |
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Physical Dimensions
PCB thickness: 1.6 mm.
Scroll Title |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TEM0005_TS_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
Scroll Title |
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
Scroll Title |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
---|
|
Date | Revision | Changes | Documentation Link |
---|
| REV01 | | REV01 |
| REV02 | - Support M2S050 -> added R29,R30, C24..C26,C31
- Added resistor R32
- Full upd LIB
| REV02 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Scroll Title |
---|
anchor | Figure_RV_HRN |
---|
title | Board hardware revision number. |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
| |
---|
diagramName | TEM0005_RV_HRN |
---|
simpleViewer | false |
---|
width | 200 |
---|
links | auto |
---|
tbstyle | hidden |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 175 |
---|
revision | 6 |
---|
|
|
Scroll Only |
---|
|
|
Document Change History
Page properties |
---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Scroll Title |
---|
anchor | Table_RH_DCH |
---|
title | Document change history. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Revision | Contributor | Description |
---|
Page info |
---|
infoType | Modified date |
---|
dateFormat | yyyy-MM-dd |
---|
type | Flat |
---|
|
| Page info |
---|
infoType | Current version |
---|
prefix | v. |
---|
type | Flat |
---|
showVersions | false |
---|
|
| Page info |
---|
infoType | Modified by |
---|
type | Flat |
---|
showVersions | false |
---|
|
| | -- | all | Page info |
---|
infoType | Modified users |
---|
type | Flat |
---|
showVersions | false |
---|
|
| |
|
Disclaimer
Include Page |
---|
| IN:Legal Notices |
---|
| IN:Legal Notices |
---|
|