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Scroll Title

anchor	Table_SIP_JTG
title	JTAG pins connection

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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sortByColumn	1
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cellHighlighting	true

JTAG Signal	B2B Connector
TMS	J1-14
TDI	J1-8
TDO	J1-10
TCK	J1-12
JTAG_EN	J1-7

Test Points

Page properties

hidden	true
id	Comments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal	B2B	Notes
10	PWR_PL_OK	J2-120

...

Scroll Title

anchor	Table_OBP
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Notes
QSPI	U3
DDR3 DDR3L SDRAM	U5
EEPROM	U4
Authentication IC	U6
Ethernet Transceiver	U1
Oscillators

Quad SPI Flash Memory

Page properties

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id	Comments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TEM0005 is equipped with a QSPI flash memory, U3 provided in order to store data and configuration.

Scroll Title

anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin

Schematic	U?? U3 Pin	Connected to	Notes

...

SPI0_SS0	nCE	FPGA Bank 2
SPI0_CLK	SCK	FPGA Bank 2
SPI0_SDO	SI/IO0	FPGA Bank 2
SPI0_SDI	SO/IO0	FPGA Bank 2

EEPROM

The TEM0005 is equipped with an EEPROM IC,U4. The two I²C signals are connected to authentication IC as well.

Scroll Title

anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

Scroll Table Layout

repeatTableHeaders
orientation	portrait
sortDirection	ASC

Scroll Title

anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin

Schematic

U??

U4 Pin	Notes
I2C0_SCL	SCL
I2C0_SDA	SDA

Scroll Title

anchor	Table_OBP_I2C_EEPROM
title	I2C address for EEPROM

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin Pin	I2C Address	Designator	Notes

DDR3 SDRAM

Page properties

hidden	true
id	Comments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

Part number:
Supply voltage:
Speed:
NOR Flash
Temperature:

Ethernet

...

anchor	Table_OBP_ETH
title	Ethernet PHY to Zynq SoC connections

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anchor	Table_OBP_CLK
title	Osillators

...

Power and Power-On Sequence

...

hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 1.5 A for system startup is recommended.

Power Consumption

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anchor	Table_PWR_PC
title	Power Consumption

...

* TBD - To Be Determined

Power Distribution Dependencies

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anchor	Figure_PWR_PD
title	Power Distribution

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Power-On Sequence

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anchor	Figure_PWR_PS
title	Power Sequency

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Scroll Only
Image Removed

Voltage Monitor Circuit

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anchor	Figure_PWR_VMC
title	Voltage Monitor Circuit

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Power Rails

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anchor	Table_PWR_PR
title	Module power rails.

...

B2B Connector JM1 Pin

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Bank Voltages

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anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

...

Bank

...

Voltage

...

VDDI1

...

hidden	true
id	Comments

...

use "include page" macro and link to the general B2B connector page of the module series,

...

Technical Specifications

Absolute Maximum Ratings

...

anchor	Table_TS_AMR
title	PS absolute maximum ratings

...

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

...

anchor	Table_TS_ROC
title	Recommended operating conditions.

...

Physical Dimensions

Module size: 56 mm × 31 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.

PCB thickness: 1.6 mm.

...

hidden	true
id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

...

anchor	Figure_TS_PD
title	Physical Dimension

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scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Image Removed

Currently Offered Variants

Page properties

hidden	true
id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

...

Revision History

Hardware Revision History

Page properties

hidden	true
id	Comments

Set correct links to download arrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD

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anchor	Table_RH_HRH
title	Hardware Revision History

...

Support M2S050 -> added R29,R30, C24..C26,C31
Added resistor R32
Full upd LIB

...

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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anchor	Figure_RV_HRN
title	Board hardware revision number.

...

Scroll Only
Image Removed

Document Change History

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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anchor	Table_RH_DCH
title	Document change history.

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Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

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Page info

infoType	Modified by
type	Flat
showVersions	false

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change list

...

all

...

Page info

infoType	Modified users
type	Flat
showVersions	false

...

Disclaimer

...

Page properties

hidden	true
id	Comments

Template Revision 2.12

Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"

HTML

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

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hidden	true
id	Comments

Important General Note:

...

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

...

Figure template:

...

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

SCL/SDA

0x70

Authentication IC

There is an Authentication IC ATECC608A provided on TEM0005, The IC is connected to I2C0 signals.

...

Table template:

Layout macro can be use for landscape of large tables

...

anchor	Table_tablename
title	Text

...

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

<type>_<main section>_<name>
- type: Figure, Table
- main section:
  - "OV" for Overview
  - "SIP" for Signal Interfaces and Pins,
  - "OBP" for On board Peripherals,
  - "PWR" for Power and Power-On Sequence,
  - "B2B" for Board to Board Connector,
  - "TS" for Technical Specification
  - "VCP" for Variants Currently in Production
  - "RH" for Revision History
- name: custom, some fix names, see below
Fix names:
- "Figure_OV_BD" for Block Diagram
- "Figure_OV_MC" for Main Components
- "Table_OV_IDS" for Initial Delivery State
- "Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
- "Table_TS_AMR" for Absolute_Maximum_Ratings
- "Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
- "Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History

...

Page properties

hidden	true
id	Comments

-----------------------------------------------------------------------

Page properties

hidden	true
id	Comments

Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...

Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.

Page properties

hidden	true
id	Comments

Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

...

hidden	true
id	Comments

Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features' must be split into 6 main groups for modules and mainboards:

SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
RAM/Storage
- Low Power DDR4 on PS
  - Data width: 32bit
  - Size: def. 2GB*
  - Speed:***
- eMMC
  - Data width: 8Bit
  - size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
  - Data width: 8bit
  - size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
  - size:*
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
Dimension
- 4 cm x 5 cm
Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination

Key Features' must be split into 6 main groups for carrier:

Modules
- TE0808, TE807, TE0803,...
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

<Replace for module use "SoC/FPGA" for Carrier "Modules">
- ...
RAM/Storage
- ...
On Board
- ...
Interface
- ...
Power
- ...
Dimension
- ...
Notes
- ...

Block Diagram

...

hidden	true
id	Comments

add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

...

anchor	Figure_OV_BD
title	TEM0005 block diagram

...

Scroll Only
Image Removed

Main Components

...

hidden	true
id	Comments

Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

...

anchor	Figure_OV_MC
title	TEM0005 main components

...

Scroll Only
Image Removed

Initial Delivery State

Page properties

hidden	true
id	Comments

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

...

Storage device name

...

Content

...

Notes

...

Quad SPI Flash

...

Configuration Signals

Page properties

hidden	true
id	Comments

Overview of Boot Mode, Reset, Enables.

...

anchor	Table_OV_BP
title	Boot process.

...

MODE Signal State

...

anchor	Table_OV_RST
title	Reset process.

...

Signal

...

Signals, Interfaces and Pins

Page properties

hidden	true
id	Comments

Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

...

anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

...

JTAG access to the TExxxx SoM through B2B connector JMX.

...

anchor	Table_SIP_JTG
title	JTAG pins connection

...

JTAG Signal

...

B2B Connector

...

MIO Pins

...

hidden	true
id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

...

anchor	Table_SIP_MIOs
title	MIOs pins

...

Test Points

...

hidden	true
id	Comments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

...

anchor	Table_SIP_TPs
title	Test Points Information

...

On-board Peripherals

Page properties

hidden	true
id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Page properties

hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

...

anchor	Table_OBP
title	On board peripherals

...

Quad SPI Flash Memory

Page properties

hidden	true
id	Comments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

...

anchor	Table_OBP_RTC
title	I2C interface MIOs and pins

...

anchor	Table_OBP_I2C_RTC
title	I2C Address for RTC

...

anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

...

anchor	Table_OBP_I2C_EEPROM
title	I2C address for EEPROM

...

LEDs

Scroll Title

anchor	Table_OBP_LEDAuth
title	On-board LEDsAuthentication IC information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator

Color

Connected to

Active Level

Note

...

Pin	Schematic	Notes
SCL	I2C0_SCL	Serial Clock
SDA	I2C1_SCL	Serial Data

DDR3L SDRAM

Page properties

hidden	true
id	Comments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? TEM0005 SoM has ??? GByte volatile DDR3 2 Gb volatile DDR3L SDRAM IC for storing user application code and data.

Part number: IS43TR16128CL-125KBLI
Supply voltage: 1.5 V
SpeedAccess:
NOR Flash
time 20 ns
Temperature:

Ethernet

...

anchor	Table_OBP_ETH
title	Ethernet PHY to Zynq SoC connections

-40 to 95 °C

Ethernet Transceiver

On board 10/100 Mbps Ethernet Transceiver U1 is provided on the module TEM0005.

...

Scroll Title

anchor	Table_OBP_CANETH
title	CAN Tranciever interface MIOsEthernet PHY to Zynq SoC connections

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank

Schematic

U?? Pin

Notes

D-Tx

Driver Input

R-Rx

Reciever Output

...

anchor	Table_OBP_CLK
title	Osillators

U1 Pin	Signal Name	Connected to
RXM/RXP	ETH1_RX	B2B, J1
TXM/TXP	ETH1_TX	B2B, J1
LED0/NWAYEN	ETH1_LED0	B2B, J1
LED1/SPEED	ETH1_LED1	B2B, J1
MDIO	ETH1_MDIO	FPGA Bank 7, U2
MDC	ETH1_MDC	FPGA Bank 7, U2
REXT	-	GND
INTRP	ETH1_INTRP	FPGA Bank 7, U2
XO/XI	-	Crystal Oscillator, Y3
nRST	ETH1_RST	FPGA Bank 7, U2
CONFIG0...2	ETH1_COL/CRC/RXDV	FPGA Bank 7, U2
TXC	ETH1_TXC	FPGA Bank 7, U2
TXEN	ETH1_TXEN	FPGA Bank 7, U2
TXD0...3	ETH1_TXD0...3	FPGA Bank 7, U2
RXD0...3	ETH1_RXD0...3	FPGA Bank 7, U2
RXC	ETH1_RXC	FPGA Bank 7, U2
RXCER	ETH1_RXCER	FPGA Bank 7, U2

Clock Sources

...

Programmable Clock Generator

There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I²C via PIN header J??. The I²C Address is 0x??.

OUT8/OUT9

Scroll Title

anchor	Table_OBP_PCLKCLK
title	Programmable Clock Generator Inputs and OutputsOsillators

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true
	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Description	Frequency	Note
Y3	Crystal Oscillator	25 MHz

U?? Pin

Signal

Connected to

Direction

Note

IN0

IN1

IN2

IN3

XAXB

SCLK

SDA

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Power and Power-On Sequence

Page properties

hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx 1.5 A for system startup is recommended.

Power Consumption

Scroll Title

anchor	Table_PWR_PC
title	Power Consumption

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Input Pin	Typical Current
VIN	TBD*

* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title

anchor	Figure_PWR_PD
title	Power Distribution

Scroll Ignore

draw.io Diagram

border	false

diagramName	TEM0005_PWR_PD
simpleViewer	false
width	639
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	3

Scroll Only

Power-On Sequence

Scroll Title

anchor	Figure_PWR_PS
title	Power Sequency

Scroll Ignore

draw.io Diagram

border	false

diagramName	TEM0005_PWR_PS
simpleViewer	false
width	639
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	1

Scroll Only

Voltage Monitor Circuit

Scroll Title

anchor	Figure_PWR_VMC
title	Voltage Monitor Circuit

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Power Rails

Scroll Title

anchor	Table_PWR_PR
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name	B2B Connector JM1 Pin	Direction	Notes
3.3V	1, 2, 3, 4	Output
VDDI6	22	Input

Bank Voltages

Scroll Title

anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank	Schematic Name	Voltage
Bank0	VDDI0	1.5V
Bank1	VDDI1	3.3V
Bank2	VDDI2	3.3V
Bank3	VDDI3	3.3V
Bank4	VDDI4	3.3V
Bank5	VDDI6	3.3V
Bank6	VDDI6	3.3V
Bank7	VDDI7	3.3V

Board to Board Connectors

Page properties

hidden	true
id	Comments

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
PD:6 x 6 SoM LSHM B2B Connectors
PD:6 x 6 SoM LSHM B2B Connectors

Include Page

	3.1 x 5.6 SoM ST5/SS5 B2B Connectors
	3.1 x 5.6 SoM ST5/SS5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Scroll Title

anchor	Table_TS_AMR
title	PS absolute maximum ratings

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Symbols	Description	Min	Max	Unit
VIN	Input Supply Voltage

-5

		V
STG_T

_STG

Storage Temperature

-55155

°C

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 15

New Version 16

Key

Test Points

Quad SPI Flash Memory

EEPROM

DDR3 SDRAM

Ethernet

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Authentication IC

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

MIO Pins

Test Points

On-board Peripherals

Quad SPI Flash Memory

LEDs

DDR3L SDRAM

Ethernet

Ethernet Transceiver

Clock Sources

Programmable Clock Generator

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

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