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The Trenz Electronic TEM0707 is an industrial-grade module for 4 x 5 Trenz Electronic modules. The TEB0707 is integrated with an Intel MAX10 FPGA and it is equipped with a Micro USB2.0 Socket, RJ45 LAN Socket, Micro USB A Socket, Micro SD Card Socket, Low and High Speed Board to Board Connectors, User LEDs, FTDI, Push Buttons and DIP Switch for controlling the SoM.
Refer to http://trenz.org/teb0707-info for the current online version of this manual and other available documentation.
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- Modules
- RAM/Storage
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48(FTDI Configuration)
- On Board
- Intel Max 10 FPGA
- FTDI FT2223
- 8x Green User LEDs
- DIP Switch
- Push Buttons
- Interface
- Gigabit RJ45 LAN socket
- SD Card socket
- Micro USB2.0 Socket
- Miceo USB A Socket
- 6x High Speed B2B Connectors,
- 1x Low Speed B2B Connector
- 4x Jumpers
- Power
- Dimension
- Notes
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JTAG Interface
JTAG access to the TExxxx attached SoM through B2B connector JMXJB2. The JTAG Enable is connected to VCC and after power on it will be enable.
| Scroll Title |
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| anchor | Table_SIP_JTGMJTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector |
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| M_TMS | JB2-94 | | M_TDI | JB2-96 | | M_TDOTCK | JB2-100 | | JTAGM_EN |
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MIO Pins
There is an Intel MAX10 provided on TEB0707 as CPLD and JTAG access to the Intel MAX10 SoC is provided through the FTDI U8.
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
| MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| anchor | Table_SIP_MIOsMJTG |
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| title | MIOs JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | NotesJTAG Signal | Connected to |
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| M_TMS | FTDI (U8) - ADBUS3 |
| M_TDI | FTDI (U8) - ADBUS1 |
| M_TDO | FTDI (U8) - ADBUS2 |
| M_TCK | FTDI (U8) - ADBUS0 |
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Micro USB2.0
Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | B2B | Notes |
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| 10 | PWR_PL_OK | J2-120 |
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| Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Test Point | Signal | Connected to | Notes |
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| TP1 | 3.3V | Regulator, U1 |
| | TP2 | VIN | Voltage Protection, U2 |
| | TP4 | IOV | Regulator, U3 |
| | TP5 | 3.3V | Power Switch, Q1 |
| | TP6 | C5VIN | Power Switch, Q2 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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