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Scroll Title
anchorTable_OV_BP
titleBoot process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MODE[0:3]

Boot ModePin LocationNote

0000

PS_JTAG

JTAGPSJTAG Interface
0010Quad SPI (32b)MIO0...12QSPI 32bit addressing
0101SD1 2.0MIO31...51SD 2.0
0111USB2.0MIO52...63Only USB2.0
Refer to CPLD Page
0001Quad SPI FlashRefer to CPLD Page
0101SD CardRefer to CPLD Page1110SD1 LS 3.0MIO39...51SD 3.0 with complaint voltage level shifter



Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

B2BI/ONote

RESETN

J1-36InputPulled up to 3.3V_CPLD


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