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title Reference IP custom blocks dependencies and connections
custom IP core block XPS_I2C_SLAVE XPS_NPI_DMA XPS_FX2 brief description forwards MicroBlaze API Commands (MB Commands) coming from the USB bus towards the MicroBlaze custom DMA between DDR SDRAM and other multiple sources; used for high speed bidirectional communication between the FPGA and a host computer (also USB host) longer dscription XPS_I2C_SLAVE custom IP core block XPS_NPI_DMA custom IP core block XPS_FX2 custom IP core block is used to deliver MB Command to FPGA's MicroBlaze soft μP (through FX22MB_REGs) and retrieve "reply" (through MB2FX2_REGs) is used to realize a FPGA  ↔ FX2 μC connection (trough I2C) (trough a 8 bit bus) is used to realize a FPGA  ↔ DRAM connection

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title Reference architecture block diagram.

XPS_I2C_SLAVE custom IP core block

It is a logic block for low speed bidirectional communication between the FPGA and a host PC. It is usually used for command, settings and status communication. It contains 6 × 32-bit memory mapped registers:

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VHDL code: here.

MicroBlaze Driver code: here.

A longer description: here.

XPS_NPI_DMA custom IP core block

It is a high speed DMA (direct memory access) engine which connects to the MPMC (Multi-Port Memory Controller) VFBC (Video Frame Buffer Controller) port. It enables high speed data streaming to/from external memory (DDR SDRAM) and multiple sources. It can be controlled by a processor using 6 × 32-bit memory mapped registers attached to the PLB (peripheral local bus). For more information about registers, see Xilinx LogiCORE IP Multi-Port Memory Controller (MPMC) data sheets (Xilinx DS643), Video Frame Buffer Controller PIM section.
When data is sent from the USB-host to a USB FX2 module high-speed endpoint (high speed communication channel), it is automatically stored into the RAM by the custom built DMA engine (XPS_NPI_DMA) at a specified buffer location. The reference design software running on the MicroBlaze verifies the transferred data at the end of transmission and sends to the USB host a notification about the data test (passed / failed).

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MicroBlaze Driver code: here.

A longer description: here.

XPS_FX2 custom IP core block

It is a logic block for high speed bidirectional communication between the FPGA and a host PC. It contains 2 kbyte FIFOs for data buffering. More information about the 5 × 32-bit memory mapped registers is contained in the #project_root#/pcores/xps_fx2_v1_00_a/doc/ folder of the reference design project folder.
When data is sent form a USB FX2 module high-speed endpoint to the USB host, it is automatically fetched from the RAM via the custom DMA engine (XPS_NPI_DMA) and forwarded to the XPS_FX2 core in 1-kbyte packets. MicroBlaze throttles the throughput to prevent XPS_FX2 TX FIFO overflow.

VHDL code: here.

MicroBlaze Driver code: here.

A longer description: here.

Source Code of the reference architecture

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