Title: Preloaded Logic Architecture Layer (in SPI Flash): Reference Architecture Layer description  
Author: Sergio Pavesi 14 11, 2013
Last Changed by: Sergio Pavesi 14 11, 2013
Tiny Link: (useful for email) https://wiki.trenz-electronic.de/x/hh2i
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Incoming Links
TE USB Suite (3)
    Page: Logic Architecture Layer (Generation 2 = Generation 3): FPGA image
    Page: Device Driver Layer
    Page: Firmware/Bitstream Tools Comparison
Hierarchy
Parent Page
    Page: Logic Architecture Layer (Generation 2 = Generation 3): FPGA image
Children (4)
    Page: XPS_FX2 custom IP core block
    Page: XPS_I2C_SLAVE custom IP core block
    Page: XPS_NPI_DMA custom IP core block
    Page: TO DELETE XPS_NPI_DMA custom IP core block
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Recent Changes
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14 11, 2013 11:00 Sergio Pavesi View Changes
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14 11, 2013 10:06 Sergio Pavesi View Changes
14 11, 2013 10:05 Sergio Pavesi  
Outgoing Links
External Links (15)
    https://github.com/Trenz-Electronic/TE-EDK-IP/tree/master/M…
    https://github.com/Trenz-Electronic/TE-EDK-IP/tree/master/M…
    https://github.com/Trenz-Electronic/TE-EDK-IP/tree/master/M…
    www.xilinx.com/support/documentation/ip_documentation/mpmc.…
    https://github.com/Trenz-Electronic/TE-EDK-IP/tree/master/M…
    https://github.com/Trenz-Electronic/TE063X-Reference-Design…
    https://wiki.trenz-electronic.de/pages/viewpage.action?page…
    https://github.com/Trenz-Electronic/TE03XX-Reference-Design…
    https://wiki.trenz-electronic.de/display/TEUSB/XPS_NPI_DMA+…
    https://wiki.trenz-electronic.de/display/TEUSB/SW+API+Layer
    https://wiki.trenz-electronic.de/display/TEUSB/XPS_I2C_SLAV…
    https://wiki.trenz-electronic.de/display/TEUSB/XPS_FX2+cust…
    https://github.com/Trenz-Electronic/TE-EDK-IP/tree/master/M…
    https://wiki.trenz-electronic.de/display/TEUSB/FX22MB_REG0_…
    https://github.com/Trenz-Electronic/TE-EDK-IP/tree/master/M…
TE USB Suite (4)     Page: TO DELETE XPS_NPI_DMA custom IP core block
    Page: XPS_I2C_SLAVE custom IP core block
    Page: XPS_FX2 custom IP core block
    Page: Logic Architecture Layer (Generation 2 = Generation 3): FPGA image