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Template Revision 3.1

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

  • Template Change history:

    • 3.02 to 3.1
      • New general notes for temperature range to "Recommended Operating Conditions"
    • 3.01 to 3.02
      • add again fix table of content with workaround to use it for pdf and wiki
      • Export Link for key features examples
        • Notes for different Types (with and without Main FPGA)
      • Export Link for Signals, Interfaces and Pins examples
        • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
    • 3.0 to 3.01
      • remove fix table of content and page layout ( split page layout make trouble with pdf export)
      • changed and add note to signal and interfaces, to on board periphery section
      • ...(not finished)
    • 2.13 to 3.00
      • → separation of Carrier/Module and evaluation kit TRM
    • 2.14 to 2.15
      • add excerpt macro to key features
    • 2.13 to 2.14
      • add fix table of content
      • add table size as macro


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

The Trenz Electronic TE0865  is an industrial/extended grade module based on Xilinx Zunq UltraScale+ MPSoC. The TE0865 is equipped with 4x 2GB DDR4 SDRAM connected to Programmable Logic(PL) and 5x 2GB DDR4 SDRAM connected to Processing System(PS), 8 GB eMMC, 2x 64MB Quad SPI Flash, Gigabit Ethernet Transceiver, USB Transceiver, Ultra micro power terminal and an Intel MAx 10 as system controller CPLD. 

Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • SoC/FPGA
    • Package: C1760
    • Device: ZU11, ZU17, ZU19*
    • Engine: EG*
    • Speed: -1, -2,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 16bit
      • Size: def. 2GB*
      • Speed: 3200 (MT/s) ***
    • Low Power DDR4 on PL
      • Data width: 16bit
      • Size: def. 2GB*
      • Speed:***
    •  eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 64MB *
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Intel Max 10 as CPLD
    • 6x MEMS Oscillator
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3340C)
  • Interface
    • 214 x PS I/Os
    • 96x HD I/Os
    • 416x HP I/Os
    • 4x PS GTR
    • 3x Samtec Accelerate HD B2B connector
    • 78x MIOs
  • Power
    • 12V input supply voltage
    • Variable Bank IO Power Input
  • Dimension
    • 7.5 cm x 10 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
titleTE0865 block diagram


Scroll Ignore
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Scroll Only

Image Added


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titleTE0865 main components


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  1. ZYNQ Ultrascale+ MPSoC FPGA, U30
  2. PL DDR4 SDRAM, U9, U10, U28, U29
  3. PS DDR4 SDRAM, U5...U8, U11
  4. Intel MAX 10 FPGA, U46
  5. eMMC RAM, U1
  6. Dual QSPI Flash, U32, U33
  7. Crypto Authentication IC, U19
  8. OPTIGA Trust M Authentication IC, U16
  9. EEPROM MAC Address, U14
  10. USB2.0 Transceiver, U2
  11. Gigabit Ethernet Transceiver, U17
  12. B2B Connector, J2
  13. B2B Connector, J3
  14. B2B Connector, J1
  15. B2B Connector, J4
  16. Power Terminal, J5

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROMProgrammed

MAC Address

System Controller CPLDProgrammedIntel MAX 10
PL DDR4 SDRAMNot Programmed
PS DDR4 SDRAMNot Programmed
eMMCNot Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.


Scroll Title
anchorTable_OV_CNTRL
titleController signal.

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Function

SchematicConnected toDirectionDescription

Boot Mode

MODE0...3B2B, J3AInput
ResetPERST0B2B, J1BInput
PGOODPG_VCCINTCPLD, U46Output
Power EnableEN_VCCINTCPLD, U46Input


Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note

Modules has mostly B2B Connector with Interface subsections

Hybride Modules have B2B Connector with Interface subsections and additional "real" connector

Carrier has  B2B connector (maybe not all interfaces like modules has) and "real" connectors

Evaluation boards has only "real" connectors

Modules with main SoC have an additional MIO section, where dedication MIO Pin assignment will be shown


Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
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titleGeneral PL I/O to B2B connectors information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
































JTAG Interface

JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

B2B Connector

TMSJ3B- D59
TDIJ3B- D57
TDOJ3B- D58
TCK

J3B- D56


JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

B2B Connector

TCK_MAX10J2B- D56
TMS_MAX10J2B- D57
TDO_MAX10J2B- D58
TDI_MAX10

J2B- D59

JTAGENPulled Up


MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Scroll Title
anchorTable_SIP_MIOs
titleMIOs pins

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MIO PinConnected toNotes
MIO0...5QSPI Flash, U32
MIO6...11QSPI, Flash, 33
MIO13...22eMMC, U1
MIO23B2B, J2AU_INIT
MIO24...25B2B, J3BI2C U via Voltage Transform, U15
MIO26...27B2B, J2AUART0_RX
MIO28...29B2B, J2AUART1_RX
MIO30...31B2B, J2AI2C M via Voltage Transform, U12
MIO32...37B2B, J2AGPIO0...5
MIO38B2B, J2AM_INIT
MIO39...42B2B, J2BSD
MIO43B2B, J2APS_RSTn
MIO44...51B2B, J2ASD
MIO52...63USB2.0, U2USB2.0
MIO64...77ETH PHY, U17ETH PHY


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Scroll Title
anchorTable_SIP_TPs
titleTest Points Information

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Test PointSignalNotes
TP1...2+12.0V
TP3...4+3.3V
TP5...6+3.3V_SW
TP7...8+2.3V
TP9...10+1.8V
TP11...12+1.8V_AUX
TP13...14+1.8V_VCCADC
TP15...16+0.85V_VCCINT
TP17...18+1.2V_PL_DDR
TP19...20+2.5V_PL_DDR
TP21...22+0.85V_GTR_AVCC_PS
TP23...24+1.8V_GTR_AVTT_PS
TP25...26+1.8V_AUX_PS
TP27...28+1.2V_PLL_PS
TP29...30+1.2V_PS_DDR
TP31...32+2.5V_PS_DDR
TP33...34VREFA_DDR_PS
TP35...36VREFA_DDR_PL
TP37...38VTT_DDR_PS
TP39...40VTT_DDR_PL
TP41...42+0.9V_GTH_AVCC
TP43...44+1.8V_GTH_AUX
TP45...46+1.2V_GTH_AVTT
TP47...48+0.9V_GTY_AVCC
TP49...50+1.8V_GTY_AUX
TP51...52+1.2V_GTY_AVTT


On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example: #ClockSources, #CPLD, #QuadSPIFlash


Scroll Title
anchorTable_OBP
titleOn board peripherals

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Chip/InterfaceDesignatorNotes
Intel MAX 10U46
PL DDR4 SDRAM

U9, U10, U28, U29


PS DDR4 RAMU5...U8, U11
Dual QSPI FlashU32, U33
eMMC RAMU1
USB2.0 TransceiverU2
Gigabit Ethernet TransceiverU17
EEPROMU14
Crypto AuthenticationU19
OPTIGA AuthenticationU16
MEMS Oscillator,



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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

CPLD

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Note

Link always to CPLD Documentation, because CPLD Firmware can be changed during the time. Describe used device type and basic Pin connection to B2B and Main FPGA


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

Scroll Table Layout
orientationportrait
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MIO PinSchematicU?? PinNotes

























Crypto Authentication


OPTIGA Authentication

EEPROM

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
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repeatTableHeadersdefault
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sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU?? PinNotes










Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM

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MIO PinI2C AddressDesignatorNotes






PL DDR4 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

PS DDR4 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature:

Ethernet

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

Scroll Table Layout
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cellHighlightingtrue

U?? Pin Signal NameConnected toSignal DescriptionNote







































































eMMC

Scroll Title
anchorTable_OBP_eMMC
titleeMMC Information

Scroll Table Layout
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SchematicU?? PinNotes








Clock Sources

Scroll Title
anchorTable_OBP_CLK
titleOsillators

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DesignatorDescriptionFrequencyNote


MHz


MHz


KHz





Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Scroll Title
anchorTable_PWR_PC
titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


Scroll Ignore
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Scroll Only


Power-On Sequence

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTE0865_PWR_PS
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision1


Scroll Only


Voltage Monitor Circuit

Scroll Title
anchorFigure_PWR_VMC
titleVoltage Monitor Circuit


Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.


Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power Rails

Scroll Title
anchorTable_PWR_PR
titleModule power rails.

Scroll Table Layout
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Power Rail Name

B2B J1 Pin

B2B J2 Pin

B2B J3 Pin

B2B J4 PinDirectionNotes
VCCIO_67D10---In
VCCIO_66D20---In
VCCIO_64D35---In

VCCIO_65

D45---In
VCCIO_91-A6,--In
VCCIO_90-B10--In
VCCIO_89-A21--In
V_IO_CFG-A45--In
+1.2V_PL_DDR-B44--Out
VCCIO_68-C29--In
VCCIO_88-D44--In
+3.3V-D60--Out
+1.8V-
D60-Out


Bank Voltages

Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
64 HPVCCIO_64max 1.8 V
65 HP VCCIO_65max 1.8 V
66 HPVCCIO_66max 1.8 V
67 HP VCCIO_67max 1.8 V
68 HPVCCIO_68max 1.8 V
69 HP VCCIO_691.2 V


70 HPVCCIO_701.2 V


71 HPVCCIO_711.2 V
88 HDVCCIO_88max 3.3VZU17 Bank 90 HD
89 HDVCCIO_88max 3.3 VZU17 Bank 91 HD
90 HDVCCIO_88max 3.3VZU17 Bank 93 HD
91 HDVCCIO_88max 3.3VZU17 Bank 94 HD
128 GTYMGTAVCC_L0.9 V
129 GTYMGTAVCC_L0.9 V
224 GTHMGTAVCC_RS0.9 V
225 GTHMGTAVCC_RS0.9 V
228 GTHMGTAVCC_RN0.9 V
229 GTHMGTAVCC_RN0.9 V
500 PSMIOVCCO_PSIO0_5001.8 V
501 PSMIOVCCO_PSIO0_501max 3.3 V
502 PSMIOVCCO_PSIO0_5021.8 V
504 PSDDRVCCO_PSDDR_5041.2 V
505 PSGTRPS_MGTRAVCC0.85 V



Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Scroll Title
anchorTable_TS_AMR
titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit




V




V




V




V




V




V




V




V




°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



°CSee  ???? datasheet.



°CSee  ???? datasheet.



Components are mainly classified in 3 temperature groups, according to range specifications: commercial: 0°C - 75°C extended: 0°C - 85°C industrial: -40°C - 85°C

Classification of the module can be locked up here: Article Number Information i.e.: TE0803-03-5D"I"21-AS (The I indicates industrial)

The actual operation temperature range depends on the FPGA/SoC design/utilization and cooling, as well as other variables. Please note: These are only indications!

Physical Dimensions

  • Module size: 75 mm × 100 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

PCB thickness: 2 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titlePhysical Dimension


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scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Scroll Title
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titleTrenz Electronic Shop Overview

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Trenz shop TE0865 overview page
English pageGerman page


Revision History

Hardware Revision History

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idComments

Set correct links to download  Carrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD
  • Example: 

    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    REV02



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anchorFigure_RV_HRN
titleBoard hardware revision number.


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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2021-04-15REV01Initial Release


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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titleDocument change history.

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infoTypeCurrent version
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  • change list

--

all

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infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

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IN:Legal Notices
IN:Legal Notices



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Table of contents

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