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Template Revision 1.0 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

Custom_table_size_100


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Important General Note:

  • Export PDF to download, if Libero or SoftConsole revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

          Scroll Title
          anchorTable_xyz
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          Scroll Table Layout
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          ExampleComment
          12



  • ...

Overview

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Notes :

This page describes in detail which software, and their respective versions, was used to generate und use the module demonstration.

Further described is how to flash the Hardware and Software Design contained in the Demo Archieve onto the TEM0001.

A brief usage introduction for each Demo is included.


The Hardware Reference Design uses these Smartfusion 2 SoC, hard Arm® Cortex®-M3 Core, Soft SDRAM Core, Soft SPI Core, COM port, Real Time Clock and the on-board LEDs via a Soft PWM Core.

The Software Designs Hello World, SF2_GNU_SC4_pwm_slow_blink and SF2_GNU_SC4_rtc_time use the Hardware Design features to a different degree. Most notably is Hello World, which utializes all features of the Hardware and is very close to the modules production test.


Refer to UPDATE-LINK/LinkText:_TEM00XY-Resources UPDATE

for the current online version of this manual and other available documentation. 

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design / does the design use


Excerpt
  • Libero 2021.2 (FPGA IDE)
  • SoftConsole 2021.1 (Software IDE)
  • UART
  • SDR
  • eNVM
  • User LED access
  • Real Time Clock

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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titleTable of Design Revision History

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DateLiberoSoftConsoleProject BuiltAuthorsDescription
2021-12-092021.22021.1NAME-OF-ZIP-ARCHIVE .zipKilian Jahn
  • Initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed
  • When known issues became known/will be noted here, remove "Non known so fare.far" and the hidden artibute of the box below.

Non known so farefar.

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Notes :  When

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Module / VariantIssues DescriptionWorkaround/SolutionTo be fixed version
NAME-of-RefDes-or-Demo





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Requirements

Software


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Notes :

  • list of software and their versions which was used to generate the desig


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titleTable of used Software and their Versions

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SoftwareVersionNote
Windows 102004 / 19041
Libero Release2021.2
SoftConsole2021.1Included in the Libero installation
Microsemi Flash Pro 5 module driver2.10.0.0Utilize onboard programmer and USB / COM port connection. Included in the Libero installation
FTDI Driver for the TEM0002 module2.12.28.0
UART / COM-port terminal
Capturing the modules messages


Hardware

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Notes :

  • list of hardware which was used to generate the design
  • ADD-IMPORTANT-Feature-of-the-FPGA, Slices, ...

Design supports following modules:

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Module ModelBoard Part Short NamePCB Revision SupportDDRembedded SRAMembedded FlashNotes
TEM0001-01A-010CSMF2000REV014 MB a 16 bit64 kB256 kB       NA


Additional hardware Requirements:

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Additional HardwareNotes
Demo host computerDemo was created and tested on windows
Micro USB to USB Type A CablePower supply,  JTAG: Programming the board, UART: Communication Interface to the board.


Content

The Trenz Electronic Reference Designs and Demos are usable with the specified Microsemi Libero / SoftConsole version. Usage of a different Microsemi Libero / SoftConsole software versions is not recommended.

Download

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Important ! :

The download is a ZIP compressed archive, it needs to be extract before usage.

Recommendation :
The path of the extracted archiev is vital for all IDE's, therefore place the extracted archiev outside the user space, e.g. "c:\Extracted_Archieve" [ Access rights / Path length limit ].

Reference Designs / Demos are available via the following link:

Design Sources

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Notes :

  • content of the zip file

Content of the zip archive "TEM0001-RefDes_V2_0x.12.2021-1923" :

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TypeLocationNotes
Libero<zip archive>
      / Libero2021.2_Hardware-Design

Libero Project containing the modules
Hardware Reference Design

SoftConsole<zip archive>
      / SoftConsole2021.1_Workspace_TEM0001
            / helloWorld
            / SF2_GNU_SC4_pwm_slow_blink
            / SF2_GNU_SC4_rtc_time

SoftConsole Workspace
contains the Software Projects :

  • Hello World
  • Blinks a user led
  • A simple clock
SoftConsole<zip archive>
      / SoftConsole2021.1_Workspace_TEM0001
            / microsemi-cortex-m3.cfg

File for software debugging in
SoftConsole via "Open On Chip Debugger"
/ OpenOCD

FlashPro Express<zip archive>
      / FlashProExpress2021.2
            / RefDes02
            / RefDes02-HelloWorld
            / RefDes02-Zerocitation

Programming Files to use in FlashPro Express.

Omittes the usage of Libero and SoftConsole for Programming.

  • Reference Hardware Design for SoC and periphery
  • Reference Hardware Design + Software Design Hello World
  • Reference Hardware Design for zeroing the eNVM



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Currently this chapter is not needed for Microsemi projects

Chapter - Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

  • Notes:

The  ... to use these Project ... they are

This Demo / Reference Design /

The Hardware and Software Reference / Demo -Designs Projects are available as a prebuild zip archive. The archive contains at least a Libero Hardware Project and a SoftConsole Workspace folder, they were created and tested in windows environment.

This SoftConsole Workspace contains the Software Project ... <Name-of-the-Software-Project> . The board configuration file "NAME-of-the-Board-config-file .cfg" is required for the usage of the Software projects via the IDE SoftConsole.


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Launch

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Note:

  • Programming and Startup procedure
  • Notes:

Executing a Reference / Demo Design on a module requires the powering of it and a JTAG or UART Connection for Programming and Communication. Often the programming is a two fold process, where the first programming configures the FPGA and the second programming flashes Software code to be executed inside the FPGA / ARM processor.

Connecting

Select a variant!

Variant without explicit power connector:
Connect the modules TYPE USB to your host pc, this enables the powering of the module and a simultaneous JTAG and UART connection .

Variant with explicit power connector:
Connect the modules TYPE USB to your host pc and power the module via its dedicated power connector (e.g. Power Jack 5 V / 2 A + inside), this enables the powering of the module and a simultaneous JTAG and UART connection .

Insert picture to ilustarte the needed connections USB/Ethernet/Power jack/... (AD-TE000XY-... .PDF / schematic picture)

Driver check

When the module is connected via USB cable to your demo host computer, in the Windows Device Manager appear the following three board driver related devices:

In section Ports (COM & LPT):

  • FlashPro5 Port (ComX)

In section Universal Serial Bus controllers:

  • USB FP5 Serial Converter A
  • USB FP5 Serial Converter B

The Device Manager is accessible via "Right mouse click context menu" from the Windows Start Menu Button. When these devices are not visible, the driver installation through libero could be faulty.

Programming Hard and Software Designs

Before flashing any design to the module, open a terminal programm (e.g. PuTTY or SmarTTY) to the boards COM port, so that when the module restarts after programming, it's messages can be captured.

Programming Variant "IDE"

The Microsemi Hardware and Software Design Tools, Libero and SoftConsole, incorporate the abillity to edit, debug and program Hardware and Software Designs. This Programming Variant is for you, when you are interessted in this.

Programming the Hardware design

To program the  Hardware Reference Design, start FPGA Design "Libero SoC v2021.2".

Scroll Title
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titleLibero GUI "Run PRGORAMM ACTION"

The Hardware Reference Design can be opened via   "Project > Open Project" in the top right corner of Libero (picture above - upper green rectangle). A file dialogue opens, point the dialogue along the extracted download to the folder containing the Hardware Reference Design.

Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ Libero-X.y_Referenz-Design\

Double left mouse click onto the project file "Referenz-Design_XY .prjx" to open it. The board is automatically selected and setup to be flashed by Libero.

In the upper left section of Libero, select the tab "Design Flow" (picture above - lover green rectangle) and flash it to the board via   "Program Design > and double left mouse click onto   "Run PROGRAM Action" (picture above - row with blue background).

Warnings should not affect the functionality of a Reference / Demo -Design.


Programming a Software project

Open SoftConsole and press "Browse..." near the right edge. A file dialogue opens, point the dialogue along the extracted download to the folder containing the SoftConsole Workspace.

Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ Softconsole-X.y-Workspace \

Confirm your selectioin by pressing "Ok" , the dialogue closes, and open The SoftConsole by pressing "Launch"

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titleSoftConsole "Select the Workspace"

Subsequently the program opens and shows the software project's who are contained inside the workspace to the left, under "Project Explorer".

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titleSoftConsole GUI

To simply run a Project, press the triangle right to the button marked with a "R" in the picture above and select a variant of the demo.

Pressing the triangle next to the button marked with "D" let you select which variant to be executed in debug mode.

Debug controls - Resume - Pause - Stop

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titleSoftConsole "Debug controlls"

Switch between Debug and Run perspective (upper right corner program window)

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titleSoftConsole "Switch GUI layout"

Programming Variant "FlashPro Express"

When you just want to run a SoC Design, this is for you.

To program a Hardware and Software Design simultaneously, open FlashPro Express. Via left click onto Open .... in the section "Job Projects" open a file dialogue. Point to

Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ FlashProExpressX.y \ Desired Demo \ JobFile . pro

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titleFlashPro Express GUI

To program the Design, press Run.

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Hardware Reference Design - Libero

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

  • Nur für Libero-Designs, die mit mittels Smart-Design erstellt wurden, ist eine solche Ansicht verfügbar

Smart Design

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titleBlock Design

Constrains

IO constrains


Code Block
languageruby
titleSoC_Dedicated.pdc
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# Microsemi I/O Physical Design Constraints file

# User I/O Constraints file 

# Version: v2021.1 2021.1.0.17

# Family: SmartFusion2 , Die: M2S010 , Package: 400 VF

# Date generated: Fri Aug 13 07:56:00 2021 

# 
# User Locked I/O Bank Settings
# 

# 
# Unlocked I/O Bank Settings
# The I/O Bank Settings can be locked by directly editing this file
# or by making changes in the I/O Attribute Editor
# 

# 
# User Locked I/O settings
# 

# 
# Dedicated Peripheral I/O Settings
# 

set_io CLK1           \
    -pinname N16      \
    -fixed yes        \
    -DIRECTION INPUT


# 
# Unlocked I/O settings
# The I/Os in this section are unplaced or placed but are not locked
# the other listed attributes have been applied
# 


#
#Ports using Dedicated Pins
#

set_io DEVRST_N       \
    -pinname U17      \
    -DIRECTION INPUT


set_io XTL            \
    -pinname Y18      \
    -DIRECTION INPUT

 


Code Block
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titleSDRAM.pdc
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# Microsemi I/O Physical Design Constraints file

# User I/O Constraints file 

# Version: v11.8 11.8.0.26

# Family: SmartFusion2 , Die: M2S010 , Package: 400 VF

# Date generated: Fri Oct 20 14:01:01 2017 


# 
# User Locked I/O Bank Settings
# 


# 
# Unlocked I/O Bank Settings
# The I/O Bank Settings can be locked by directly editing this file
# or by making changes in the I/O Attribute Editor
# 


# 
# User Locked I/O settings
# 

set_io {BA[0]}         \
    -pinname W10       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {BA[1]}         \
    -pinname V12       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io CAS_N           \
    -pinname Y12       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io CKE             \
    -pinname Y13       \
    -fixed yes         \
    -DIRECTION OUTPUT





set_io {CS_N[0]}       \
    -pinname R13       \
    -fixed yes         \
    -DIRECTION OUTPUT






set_io {DQ[0]}        \
    -pinname F1       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[1]}        \
    -pinname G1       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[2]}        \
    -pinname E2       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[3]}        \
    -pinname G2       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[4]}        \
    -pinname E3       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[5]}        \
    -pinname G3       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[6]}        \
    -pinname F3       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[7]}        \
    -pinname F4       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[8]}        \
    -pinname J7       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[9]}        \
    -pinname G6       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[10]}       \
    -pinname F6       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[11]}       \
    -pinname H5       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[12]}       \
    -pinname H6       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[13]}       \
    -pinname H4       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[14]}       \
    -pinname F5       \
    -fixed yes        \
    -DIRECTION INOUT


set_io {DQ[15]}       \
    -pinname G4       \
    -fixed yes        \
    -DIRECTION INOUT





set_io {DQM[0]}        \
    -pinname E5        \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {DQM[1]}        \
    -pinname F7        \
    -fixed yes         \
    -DIRECTION OUTPUT






set_io RAS_N           \
    -pinname U13       \
    -fixed yes         \
    -DIRECTION OUTPUT





set_io {SA[0]}         \
    -pinname U11       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[1]}         \
    -pinname U12       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[2]}         \
    -pinname V11       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[3]}         \
    -pinname Y10       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[4]}         \
    -pinname W15       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[5]}         \
    -pinname U14       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[6]}         \
    -pinname Y15       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[7]}         \
    -pinname W14       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[8]}         \
    -pinname T15       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[9]}         \
    -pinname W13       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[10]}        \
    -pinname T13       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[11]}        \
    -pinname V14       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[12]}        \
    -pinname V15       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io {SA[13]}        \
    -pinname Y16       \
    -fixed yes         \
    -DIRECTION OUTPUT



set_io WE_N            \
    -pinname R12       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io SDRCLK_OUT      \
    -pinname T14       \
    -fixed yes         \
    -DIRECTION OUTPUT






Code Block
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titleSPI.pdc
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collapsetrue
# Microsemi I/O Physical Design Constraints file

# User I/O Constraints file 

# Version: v2021.1 2021.1.0.17

# Family: SmartFusion2 , Die: M2S010 , Package: 400 VF

# Date generated: Sat Jul 24 11:29:36 2021 

# 
# User Locked I/O Bank Settings
# 

# 
# Unlocked I/O Bank Settings
# The I/O Bank Settings can be locked by directly editing this file
# or by making changes in the I/O Attribute Editor
# 

# 
# User Locked I/O settings
# 

set_io SPISCLKO        \
    -pinname P18       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io SPISDI         \
    -pinname K16      \
    -fixed yes        \
    -DIRECTION INPUT


set_io SPISDO          \
    -pinname P19       \
    -fixed yes         \
    -DIRECTION OUTPUT


set_io SPISS           \
    -pinname K15       \
    -fixed yes         \
    -DIRECTION OUTPUT





Code Block
languageruby
titleLEDs_Button.pdc
linenumberstrue
collapsetrue
# SMF2000 Board Pinout, 2018-11-27

# LED1-LED8
set_io {PWM[0]} -pinname E18 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[1]} -pinname R17 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[2]} -pinname R18 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[3]} -pinname T18 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[4]} -pinname U18 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[5]} -pinname R16 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[6]} -pinname E1 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16
set_io {PWM[7]} -pinname D2 -fixed yes -iostd LVCMOS33 -OUT_DRIVE 16

#USER_LED
set_io {USER_LED} -pinname G17 -fixed yes -iostd LVCMOS33 -DIRECTION OUTPUT

# USER_BTN
set_io taster -pinname B19 -fixed yes -iostd LVCMOS33 -RES_PULL Up

Clock constrains


Code Block
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titleuser_clock_constraints.sdc
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create_clock -name {FCCC_C0_0__FCCC_C0_0__GL0_net} -period 10 -waveform {0 5 } [ get_nets { FCCC_C0_0/FCCC_C0_0/GL0_net } ]
create_clock -name {FCCC_C1_0__GL0_net} -period 250 -waveform {0 125 } [ get_nets { FCCC_C1_0/FCCC_C1_0/GL0_net } ]
create_clock -name {XTL} -period 83.3333 -waveform {0 41.6667 } [ get_ports { XTL } ]
create_clock -name {OSC_C0_0__OSC_C0_0__RCOSC_25_50MHZ_O2F} -period 20 -waveform {0 10 } [ get_pins { FCCC_C0_0/FCCC_C0_0/CCC_INST/RCOSC_25_50MHZ } ]
create_clock -name {CLK1} -period 83.3333 -waveform {0 41.6667 } [ get_ports { CLK1 } ]


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Software Design - SoftConsole

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Note:
  • optional chapter separate

  • sections for different apps

  • Notes:

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

  • Notes:

Application

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  • Describe the Designs
  • How to use
  • What to expect 

Demo Hello World

The demo project ... .

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titleCOM-port Terminal Webserver "Welcome / IP -message"


Sub chapter

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anchorFigure_7
titleSoftConsole "main.c - Set IP"


Text ... .

Reference Design - ...

Text ...
Scroll Title
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titleCOM-port Terminal "Hello World loop"

The demo project ... .

Scroll Title
anchorFigure_6
titleCOM-port Terminal Webserver "Welcome / IP -message"


Sub chapter

Scroll Title
anchorFigure_7
titleSoftConsole "main.c - Set IP"


Text ... .


Scroll Title
anchorFigure_9
titleCOM-port Terminal "Hello World loop"

Demo SF2_GNU_SC4_rtc_time

The demo project ... .

Scroll Title
anchorFigure_6
titleCOM-port Terminal Webserver "Welcome / IP -message"


Sub chapter

Scroll Title
anchorFigure_7
titleSoftConsole "main.c - Set IP"


Text ... .

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Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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DateDocument Revision

Authors

Description

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

  • Libero12.4 release
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

--


Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices











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