JTAG Chain multiplexer. Low FPGA, High CPLD. For module with CPLD only.
Connect Pulldown on carrier. DIP switch possible.
SC_EN1
JM1-28
JB1-27
in
Module power. Set high to enable module power. Note: Power management depends on module. Sometimes this is a only used as Power ON Reset like SC_nRST
Connect Pullup on carrier. DIP switch possible
SC_NOSEQ
JM1-7
JB1-8
in / inout
Module Power management. Set high to disable CPLD power management. Note: Power management depends on module and not all modules support extended power management with CPLD.
Connect Pullup or Pulldown on carrier. DIP switch possible.
SC_PGOOD
JM1-30
JB1-29
out / inout
Power Good signal. Is Low, if SC_EN1 is set to zero or if power is not ready, otherwise high impedance output. Note: Power management depends on module.
Connect Pullup on carrier. Do not use this signal to enable FPGA Bank voltages. It's only for monitoring. To Enable FPGA Banks, use 3.3V(PWR_M1) or 1.8V(PWR_M2) module output.
SC_BOOTMODE
JM1-32
JB1-31
in
Boot Mode selection Pin for Zynq module only. Default low for primary SD boot and high for primary QSPI boot. Note: Depends also on module CPLD firmware
Connect Pullup on carrier. DIP switch possible.
SC_nRST
JM2-18
JB2-17
in
Low active module reset. Pin force Power one reset on FPGA/SoC. Note: Depending from module CPLD or voltage supervisor is used.
Connect Pullup on carrier. DIP switch possible.
Note
It's planned to use SC_PGOOD of also additional Boot Mode Pin (Pin is bidirectional, pull up or force to zero), to additionally set JTAG only boot mode (to avoid programming problems with some vivado versions, see: AR#00002 - QSPI Programming issues)