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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
Date | Version | Changes | Author |
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2022-01-25 | 3.1.10 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1.9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | - Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma |
| 3.1.3 | | ma |
| 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.scr description
- added USB for programming
| ma |
| 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
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| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
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Refer to http://trenz.org/te0717-info for the current online version of this manual and other available documentation.
This example showcases a simple MicroBlaze Design that executes in an endless loop letting the red LED blink and prints "Hello Trenz Module TE0717" via UART for 10 minutes.
Key Features
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Notes : - Add basic key features, which can be tested with the design
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Excerpt |
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- Vitis/Vivado 2021.2
- MicroBlaze
- UART
- QSPI Flash
- HyperRAM
- SPI ELF Bootloader
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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title-alignment | center |
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title | Design Revision History |
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cellHighlighting | true |
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Date | Vivado | Project Built | Authors | Description |
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2022-06-20 | 2021.2 | TE0717-test_board_noprebuilt-vivado_2021.2-build_14_20220628114204.zip TE0717-test_board-vivado_2021.2-build_14_20220628114204.zip | Waldemar Hanemann | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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anchor | Table_KI |
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title-alignment | center |
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title | Known Issues |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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anchor | Table_SW |
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title-alignment | center |
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title | Software |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Software | Version | Note |
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Vitis | 2021.2 | needed, Vivado is included into Vitis installation |
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Hardware
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Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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anchor | Table_HWM |
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title-alignment | center |
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title | Hardware Modules |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0717-01-P1C-5-A | 01_100_1C_8MB | REV01 | Hyperram 8MB | 8MB | --- | --- |
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*used as reference |
Design supports following carriers:
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anchor | Table_HWC |
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title-alignment | center |
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title | Hardware Carrier |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Carrier Model | Notes |
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TEB0717 |
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*used as reference |
Additional HW Requirements:
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anchor | Table_AHW |
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title-alignment | center |
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title | Additional Hardware |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices
Design Sources
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anchor | Table_DS |
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title-alignment | center |
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title | Design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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Additional Sources
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anchor | Table_ADS |
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title-alignment | center |
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title | Additional design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebuilt content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
Create hardware description file (.xsa file) and export to prebuilt folder
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::hw_build_design -export_prebuilt |
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
- Generate Programming Files with Vitis
Run on Vivado TCL:
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language | py |
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theme | Midnight |
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title | Script generates applications and bootable files, which are defined in "sw_lib\apps_list.csv" |
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TE::sw_run_vitis -all |
- Copy "\prebuilt\software\<short name>\hello_te0717.elf" into "\firmware\microblaze_0\"
- Regenerate Vivado Project or Update Bitfile only, with new "hello_te0717.elf"
Note |
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TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Launch
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Note: - Programming and Startup procedure
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script programs .mcs-File on QSPI flash) |
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TE::pr_program_flash -swapp hello_te0717 |
- Press the reset button to start to start the application and see the output in the console
JTAG
- Connect JTAG and power on PCB
- Open Vivado HW Manager
- Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info |
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Note: See TRM of the Carrier, which is used. |
Power On PCB
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1. FPGA Loads Bitfile(spi bootloader included) from Flash 2. The spi bootloader loads the hello_te0717.elf application from address 0x005e0000 to RAM 23. Hello Trenz will be run on UART console for 10 minutes. info: Do not reboot, if Bitfile programming over JTAG is used as programming method. UARTOpen Serial Console (e.g. putty) - Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
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This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
... |
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- LED2 (green LED)
- reset MicroBlaze (active low)
- Monitoring:
- Reset of Periphery and MicroBlaze
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anchor | Figure_VHM |
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title-alignment | center |
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title | Vivado Hardware Manager |
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System Design - Vivado
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Block Design
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design |
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Constraints
Basic module constraints
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language | ruby |
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title | _i_bitgen_common.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
#
#
#
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Design specific constraints
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language | ruby |
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title | _i_io.xdc |
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set_property PACKAGE_PIN G11 [get_ports clk_100m]
set_property IOSTANDARD LVCMOS33 [get_ports clk_100m]
set_property IOSTANDARD LVCMOS33 [get_ports {LED1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED2[0]}]
set_property PACKAGE_PIN D14 [get_ports {LED1[0]}]
set_property PACKAGE_PIN C14 [get_ports {LED2[0]}] |
Code Block |
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language | ruby |
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title | _i_hyperram.xdc |
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set_property PACKAGE_PIN F13 [get_ports HB_CLK0_0]
#set_property PACKAGE_PIN A14 [get_ports HB_CLK0n_0]
set_property PACKAGE_PIN A13 [get_ports {HB_dq_0[0]}]
set_property PACKAGE_PIN B13 [get_ports {HB_dq_0[1]}]
set_property PACKAGE_PIN D12 [get_ports {HB_dq_0[2]}]
set_property PACKAGE_PIN D13 [get_ports {HB_dq_0[3]}]
set_property PACKAGE_PIN A12 [get_ports {HB_dq_0[4]}]
set_property PACKAGE_PIN G14 [get_ports {HB_dq_0[5]}]
set_property PACKAGE_PIN F14 [get_ports {HB_dq_0[6]}]
set_property PACKAGE_PIN B14 [get_ports {HB_dq_0[7]}]
set_property PACKAGE_PIN E13 [get_ports HB_RWDS_0]
set_property PACKAGE_PIN E12 [get_ports HB_CS1n_0]
set_property PACKAGE_PIN F12 [get_ports HB_RSTn_0]
#set_property PACKAGE_PIN A18 [get_ports HB_CS0n_0 ]
#set_property PACKAGE_PIN J18 [get_ports HB_INTn_0 ]
#set_property PACKAGE_PIN C17 [get_ports HB_RSTOn_0]
#
# FPGA Pin Voltage assignment
#
set_property IOSTANDARD LVCMOS33 [get_ports HB_CLK0_0]
#set_property IOSTANDARD LVCMOS33 [get_ports HB_CLK0n_0]
set_property IOSTANDARD LVCMOS33 [get_ports {HB_dq_0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports HB_CS1n_0]
set_property IOSTANDARD LVCMOS33 [get_ports HB_RSTn_0]
set_property IOSTANDARD LVCMOS33 [get_ports HB_RWDS_0]
#set_property IOSTANDARD LVCMOS18 [get_ports HB_CS0n_0]
#set_property IOSTANDARD LVCMOS18 [get_ports HB_INTn_0]
#set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTOn_0]
#set_property PULLUP true [get_ports HB_RSTOn_0]
#set_property PULLUP true [get_ports HB_INTn_0]
#
#Hyperbus Clock - change according to clk pin on PLL
#
#create_generated_clock -name clk_0 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock clk_100m [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0]
#create_generated_clock -name clk_90 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock clk_100m [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT1]
#create_generated_clock -name clk_180 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock clk_100m [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT2]
#
#100Mhz clock freqeuncy - change accordingly
#
set hbus_freq_ns 10
set dqs_in_min_dly -0.5
set dqs_in_max_dly 0.5
set HB_dq_ports [get_ports HB_dq_0[*]]
#
#Create RDS clock and RDS virtual clock
#
create_clock -period $hbus_freq_ns -name rwds_clk [get_ports HB_RWDS_0]
create_clock -period $hbus_freq_ns -name virt_rwds_clk
#
#Input Delay Constraint - HB_RWDS-HB_DQ
#
set_input_delay -clock [get_clocks virt_rwds_clk] -max ${dqs_in_max_dly} ${HB_dq_ports}
set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -max ${dqs_in_max_dly} ${HB_dq_ports} -add_delay
set_input_delay -clock [get_clocks virt_rwds_clk] -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay
set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay
set_multicycle_path -setup -end -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] 0
set_multicycle_path -setup -end -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] 0
set_false_path -fall_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -setup
set_false_path -rise_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -setup
set_false_path -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -hold
set_false_path -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -hold
#set_false_path -from [get_clocks clk_0] -to [get_clocks rwds_clk]
#set_false_path -from [get_clocks rwds_clk] -to [get_clocks clk_0]
set_false_path -from [get_clocks rwds_clk] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks rwds_clk]
#
#Output Delay Constraint - HB_CLK0-HB_DQ
#
create_generated_clock -name HB_CLK0_0 -source [get_pins */*/*/U_IO/U_CLK0/dq_idx_[0].ODDR_inst/C] -multiply_by 1 -invert [get_ports HB_CLK0_0]
set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports}
set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports}
set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports} -clock_fall -add_delay
set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports} -clock_fall -add_delay
set_false_path -from [get_pins */*/*/U_HBC/*/dq_io_tri_reg/C] -to ${HB_dq_ports}
#set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_1_reg/CLR]
#set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_2_reg/CLR]
#set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_3_reg/CLR]
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Software Design - Vitis
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For Vitis project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2021.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: fsblTE modified 2021.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
fsbl_flashTE modified 2021.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2021.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
Hello TE0717
Trenz Hello World example as endless loop
Template location: \sw_lib\sw_apps\hello_te0717
Here the The printed Text and the blinking of the red LED1 can be changedmodified
spi_bootloader
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the hello_te0717.elf from QSPI-Flash to RAM.
Descriptions:
- Modified Files: bootloader.c
- Changes:
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
App. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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title | Document change history. |
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prefix | v. |
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type | Flat |
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type | Flat |
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dateFormat | yyyy-MM-dd |
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Legal Notices
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| IN:Legal Notices |
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| IN:Legal Notices |
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