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The Trenz Electronic teCORE™ IP "AXI4-Stream TLAST ControlEFUSE_USR" is designed to be interfaced to two AXI4-Stream interfaces. This core does add generated TLAST pulses at determined intervals.provide simple access to 7-Series EFUSE_USR Primitive.
| teCORE™ IP Facts Table | |
|---|---|
| Supported Device Family | Zynq -7000, 7 Series |
| Supported User Interfaces | AXI4-Stream |
| Resources1 DSP48 | EFUSE_USR |
| Provided with Core | |
| Documentation | Product Guide |
| Design Files | VHDL Source Code |
| Tested Design Flows | |
| Design Entry | Vivado Design Suite, IP Integrator |
| Simulation | Vivado Simulator |
| Synthesis | Vivado Synthesis |
| Support | |
| Provided by Trenz Electronic GmbH | |
Overview
Feature Summary
- AXI4-Stream slave for inputWrapper for EFUSE_USR Primitive
- AXI4-Stream master for output
- Selectable input/output data width 8-256 bits
- Fixed or variable TLAST repeat period
- or
- Direct 32 bit output port
Applications
- Data acquisition
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The following sections detail the performance of the core.
Maximum Frequencies
The maximum achievable clock frequency may vary. It is expected that this IP core can run at 250MHz in any 7-Series FPGAMaximum Frequency is not applicable as this core provide only static output values.
Latency
There is no added latencyLatency is not applicable as this core provide only static output values.
Throughput
There is no degradation of the throughput introduced by this IP CoreThroughput is not applicable as this core provide only static output values.
Resource Utilization
This core does not use any dedicated I/O or CLK resources.
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| LUTs | FFs | DSP48E1 | EFUSE_USR | ||
|---|---|---|---|---|---|
| 0 | 0 | 8-256 | tbd | tbd | 1 |
Overview
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