Page History
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Template Change history:
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Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB 2.0 PHY, one GByte LPDDR4 SDRAM, 64 MByte SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.
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- SoC/FPGA
- Device: MPFS250T / MPFS160T / MPFS095T / MPFS025T 1)
- Device Family: -T / -TL / -TS / -TLS 1)
- Speedgrade: Blank / -1 1)
- Temperature Range: Extended / Industrial 1)
- Package: FCVG484Industrial-grade Microsemi Polarfire SoC MPFS250T-1FCVG484I
- RAM/Storage
- 1 GByte LPDDR4 2)
- 64 MByte SPI Flash Memory 2)
- EEPROM with MAC address
- On BoardOn Board
- System Controller CPLD
- MAC address serial EEPROM
- 10/100/1000 Mbps Gigabit Ethernet PHY
- Highly Integrated Full-Featured Hi-Speed USB 2.0 ULPI Transceiver
- Trenz 4 x 5 module socket connectors (3x Samtec LSHM series connectors)
- Power
- On-board DC-DC converter
- Dimension
- 40 mm x 50 mm
Block Diagram
- Oscillator
- Interface
- 3 x B2B Connector (LSHM)
up to 118 FPGA IOs
- GPIO: 84
- HSIO: 34
up to 14 MSSIO
- 1 SGMII
- 4 MGT
- SDIO, USB, ETH, UART, I2C, JTAG, CONFIG
- 3 x B2B Connector (LSHM)
- Power
- 3.3 V power supply via B2B Connector needed 3).
- Dimension
- 40 mm x 50 mm
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. Attention: IO number connected to B2B connector depends on the used device!
2) Please, take care of the possible assembly options.
3) A higher or lower input voltage may be possible.
Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
anchor | Figure_OV_BD |
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title-alignment | center |
title | TEM0007 block diagram |
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Main Components
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- Microsemi Polarfire SoC MPFS250T, U2
- 1 GByte LPDDR4 SDRAM, U6
- Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U7
- Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver, U11
- Lattice Semiconductor MachXO2 System Controller CPLD, U1
- B2B Connector Samtec Razor Beam, JM1...3, JM2, JM3
- EEPROM, U10
- Serial NOR Flash, U3
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Signals, Interfaces and Pins
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Test Point | Signal | Notes1) | TP1 |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section. Example:
1) Direction:
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: | ||||||
Chip/Interface | Designator | Connected To | Notes | ETH PHY | U10 |
| Gigabit ETH PHY
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Chip/Interface | Designator | Connected To | Notes |
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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals |
Configuration and System Control Signals
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title | Controller signal. |
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Signal Name
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1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here.
Link to Schematics, for power images or more details |
Power Rails
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id | Comments |
List of all power rails which are accessible by the customer
- Main Power Rails and Variable Bank Power
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example:
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anchor | Table_PWR_PR |
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title-alignment | center |
title | Module power rails. |
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1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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List baseboard design hints for final baseboard development. | ||||
For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals |
Configuration and System Control Signals
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
Board to Board Connectors
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id | Comments |
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use "include page" macro and link to the general B2B connector page of the module series,
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Technical Specifications
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List of all power rails which are accessible by the customer
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Absolute Maximum Ratings *)
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anchor | Table_TS_AMR |
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title-alignment | center |
title | Absolute maximum ratings |
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*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
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anchor | Table_TS_ROC |
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title-alignment | center |
title | Recommended operating conditions. |
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Physical Dimensions
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
PCB thickness: ?? mm.
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id | Comments |
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
Note |
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" . |
1) Direction:
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Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here.
Link to Schematics, for power images or more details |
Power Rails
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List of all power rails which are accessible by the customer
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1) Direction:
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Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
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1) A higher or lower input voltage may be possible. |
Board to Board Connectors
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Technical Specifications
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 | ||||
List of all power rails which are accessible by the customer
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Absolute Maximum Ratings *)
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Trenz shop TEM0007 overview page | ||||||||||||||||||
English page | German page |
Revision History
Hardware Revision History
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id | Comments |
Set correct links to download Carrier, e.g. TE0706 REV02:
TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents
Note:
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Example:
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- Resistors R14 and R15 was replaced by 953R (was 5K1)
- Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
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anchor | Figure_RV_HRN |
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title-alignment | center |
title | Board hardware revision number. |
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anchor | Table_RH_HRH |
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title-alignment | center |
title | Hardware Revision History |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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anchor | Table_RH_DCH |
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title-alignment | center |
title | Document change history. |
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- Initial Release
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all
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Disclaimer
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ED: TODO → Following needs to be updated to new TRM style.
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General SoC I/O to B2B connectors information |
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JTAG Interface
JTAG access to the TEM0007 SoM through B2B connector JM2.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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JM2-99
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Pulled Low: Microsemi Polarfire SoC
Pulled High: Lattice MachXO CPLD
UART Interface
The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
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anchor | Table_OBP_UART |
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title | UART interface description |
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SDIO Interface
The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
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anchor | Table_OBP_SDIO |
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title | SDIO interface description |
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MSSIO Interface
The MSSIO interface is connected from the Polarfire SoC to the B2B connector.
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anchor | Table_OBP_MSSIO |
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title | MSSIO interface description |
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SGMII Interface
The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.
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anchor | Table_OBP_SGMII |
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title | SGMII interface description |
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MGT Lanes
There are four MGT (Multi Gigabit Transceiver) lanes and two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:
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anchor | Table_SIP_MGT |
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title | MGT Lanes Connection |
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Lane
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Schematic
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Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY SGMII interface is connected to the Polarfire SoC.
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anchor | Table_OBP_ETH |
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title | Gigabit Ethernet pin description |
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System Controller CPLD I/O Pins
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
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hidden | true |
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id | Comments |
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
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*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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anchor | Table_OBP_SC |
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title | System Controller CPLD special purpose pin description |
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- 11
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USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).
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anchor | Table_OBP_USB |
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title | General Overview of the USB PHY Signals |
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DP - 18,
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OTG-D_P
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Test Points
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anchor | Table_OBP_TestPoints |
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title | Test Points Information |
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On-board Peripherals
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Notes :
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Polarfire SoC connections |
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Bank 5 - N6
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SGMII0_IN_P
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U7 - 1
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Bank 5 - L5
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SGMII0_OUT_P
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U7 - 4
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USB PHY
Hi-speed USB ULPI PHY (U11) is provided with USB3320 from Microchip. The ULPI interface is connected to the Polarfire SoC via MSSIO14...25 bank 2. The I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U12).
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anchor | Table_OBP_USB |
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title | USB PHY to Polarfire SoC connections |
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U2 - G4
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OTG-STP
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U11 - 29
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U2 - F1
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OTG-DIR
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U11 - 31
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OTG_DATA0
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LPDDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: +1.8 V / +1.1 V
- Speed: 1600 MHz
- Temperature: Industrial (-40°C to +85°C)
EEPROM
There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MSSIOs and pins |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEM0007 is equipped with a MT25QU512ABB8E12-0SIT flash memory chip, U3, which provided storage for FPGA configuration files. After configuration, the remaining free memory can be used for application data storage.
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anchor | Table_OBP_SPI |
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title | SPI Flash interface pins |
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Oscillators
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anchor | Table_OBP_CLK |
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title | Osillators |
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Power and Power-On Sequence
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hidden | true |
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id | Comments |
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Note |
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Only |
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Power-On Sequence
The power sequence is the recommended one. The final sequence depends on the system controller.
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Only |
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Voltage Monitor Circuit
The TEM0007 delivers two voltage monitor circuits. The first circuit is responsible for the selection of voltage "VDDAUX1". This voltage is selected on the basis of the voltage of "VCCIOB". If "VCCIOB" is higher than 2.9 V, "VDDAUX1" should be +3.3 V. If it is smaller, "VDDAX1" should be +2.5 V. The second circuit monitors the +1.0 V power rail. According to this rail, the reset is set/unset to realize a brown-out detection. Furthermore, a possibility for a manual reset is available.
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Scroll Only |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | Direction | Notes | ||||||||||||||
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board | ||||||||||||||
3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board | ||||||||||||||
3.3VIN | - | 91 | Output | JTAG reference voltage | ||||||||||||||
+1.8V | 39 | - | Output | Internal +1.8V voltage level | ||||||||||||||
VCCIOB | - | 1, 3 | Input | General purpose I/O bank voltage | ||||||||||||||
VCCIOD | - | 7, 9 | Input | High speed I/O bank voltage (max. +1.8 V) | ||||||||||||||
+3.3V | - | 10, 12 | Output | Internal +3.3 V voltage level |
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1) Higher and lower values may be possible. For more information consult schematic and according datasheets. |
Physical Dimensions
Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.74 mm.
Page properties | ||||
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| ||||
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
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Scroll Title | ||||||
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orientation | portrait | |||||
sortDirection | ASC | |||||
repeatTableHeaders | default | style | widths | |||
sortByColumn | 1 | |||||
sortEnabled | false | |||||
cellHighlighting | true | |||||
Bank | Schematic Name | Voltage | Notes | |||
Bank 0 HSIO | VCCIOD | Variable | max. voltage +1.8 V | |||
Bank 1 GPIO | VCCIOB | Variable | max. voltage +3.3 V | Bank 2 MSSIO | +3.3V | +3.3 V | Bank 3 | +1.8V | +1.8 V | Bank 4 MSSIO | +3.3V | +3.3 V | Bank 5 | +3.3V | +3.3 V | Bank 6 MSS DDR | +1.1V_LPDDR4 | +1.1 V |
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hidden | true |
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id | Comments |
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use "include page" macro and link to the general B2B connector page of the module series,
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Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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Revision History
Hardware Revision History
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Set correct links to download Carrier, e.g. TE0706 REV02: TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents Note:
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Technical Specifications
Absolute Maximum Ratings
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title | Absolute maximum ratings |
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VCCIOB
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Recommended Operating Conditions
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Parameter | Min | Max | Units | Reference Document | ||||||||||||
VIN | 2.7 | 5.5 | V | See EN6363Q, EP53A7LQI, and EP53A7HQI datasheets. | ||||||||||||
3.3VIN | 3.14 | 3.46 | V | See 88E1512 datasheet. | ||||||||||||
VCCIOB | 1.14 | 3.465 | V | See MPFS250T datasheet. | ||||||||||||
VCCIOD | 1.14 | 1.89 | V | See MPFS250T datasheet. |
Physical Dimensions
Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.74 mm.
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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Disclaimer
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title | Physical Dimension |
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