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Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation.

 



The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GByte of DDR3 SDRAM, 32MBytes of SPI Flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

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Table 4: MGT lanes overview.

 


Below are listed MGT bank reference clock sources.

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Table 6: JTAG interface signals. 


Note
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation.

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SourceSignalFrequencyDestinationPin NameNotes
U18CLK25.000000 MHzU10IN3 
U9CLK25.000000 MHzU7XTAL_IN 
U11

PS-CLK

33.333333 MHz

U5

PS_CLK_500

Zynq SoC PS subsystem main clock.

U15

CLK

52.000000 MHz

U6

REFCLK

USB3320C PHY reference clock.

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Figure 4: TE0820-02 power-on sequence diagram. 


For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up

Warning

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (3.3V (JM2-10, 12) or 1.8V(JM1-39) output) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

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B2B Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Note
VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
VCCIO139, 11-InputHigh range bank voltage.
VCCIO34-5Input

TE0715-xx-15: high range bank voltage.

TE0715-xx-30: high performance bank voltage.
VCCIO35-7, 9Input

TE0715-xx-15: high range bank voltage.

TE0715-xx-30: high performance bank voltage.
VBAT_IN79-InputRTC battery-buffer supply voltage.
3.3V-10, 12OutputInternal 3.3V voltage level.
1.8V39-OutputInternal 1.8V voltage level.
DDR_PWR-19OutputInternal 1.5V or 1.35V voltage level, depends on revision.
VREF_JTAG 
91OutputJTAG reference voltage (3.3V).

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Variants Currently in Production

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Temperature

Range

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B2B Connector

Height

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Trenz shop TE0715 overview page
English pageGerman page

Table 18: TE0715 variants Table 18: TE0715 variants currently in production.

Technical Specifications

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Table 19: TE0715 module absolute maximum ratings.

 


Note
Assembly variants for higher storage temperature range are available on request.

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ParameterMinMaxUnitsNotesReference Document
VIN supply voltage2.55.5V 

3.3VIN supply voltage3.1353.465V 

VBAT_IN supply voltage2.75.5V 

PL I/O bank supply voltage for HR

I/O banks (VCCO)

1.143.465V 
Xilinx datasheet DS191

PL I/O bank supply voltage for HP

I/O banks (VCCO)

1.141.89V

TE0715-xx-15 does not have

HP banks

Xilinx datasheet DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheet

Xilinx datasheet DS191

or DS187

I/O input voltage for HP I/O banks(*)(*)V

TE0715-xx-15 does not have

HP banks

(*) Check datasheet

Xilinx datasheet DS191
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 

Table 20: TE0715 module recommended operating conditions.

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DateRevision

Notes

Link to PCNDocumentation Link
2016-06-2104Second production releaseClick to see PCNTE0715-04
-03First production release 
TE0715-03
-02Prototypes 
TE0715-02
-

01

Prototypes

Prototypes



Table 21: TE0715 module hardware revision history.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Link to shop production list
  • Change normal Bank power note to important note

v.85John Hartfiel
  • Replace B2B connector section
2017-09-10v.82Jan Kumann
  • Document template revision added.
  • Revised block diagram with new I2C part.
  • Power distribution diagram added.
  • Power-on sequence diagram added.
  • Sections rearranged, some missing ones added.
  • Weight section removed.
2017-06-07

v.64

Jan Kumann
  • Minor formatting.
2017-03-02

v.59

Thorsten Trenz
  • Corrected boot mode table.
2017-02-10

v.58

Thorsten Trenz
  • Corrected PLL initial delivery state.
2017-01-25
v.55

 


Jan Kumann
  • New block diagram.
2017-01-14

v.50

Jan Kumann
  • Product revision 04 images added.
  • Formatting changes and small corrections.
2016-11-15

v.45

Thorsten Trenz
  • Added B2B Connector section.
2016-10-18
v.40

Ali Naseri

  • Added table "power rails".
2016-06-28
v.38

 

Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann

  • New overall document layout with shorter table of contents.
  • Revision 01 PCB pictures replaced with the revision 03 ones.
  • Fixed link to Master Pin-out Table.
  • New default MIO mapping table design.
  • Revised Power-on section.
  • Added links to related Xilinx online documents.
  • Physical dimensions pictures revised.
  • Revision number picture with explanation added.
2016-04-27v.33

Thorsten Trenz, Emmanuel Vassilakis

  • Added table "Recommended Operating Conditions".
  • Storage Temperature edited.
2016-03-31v.10

Philipp Bernhardt, Antti Lukats

  • Initial version.

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