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changes.mady.by.user John Hartfiel

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New Version Current

changes.mady.by.user Vadim Yunitski

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Key

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  • Formatting was changed.
Comment: Updated Key Features: DCDC converters info

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  • Industrial-grade Xilinx Zynq-7000 SoC (XC7Z015, XC7Z030)

  • Rugged for shock and high vibration
  • 2 × ARM Cortex-A9
  • 10/100/1000 Mbps Ethernet transceiver PHY
  • MAC address EEPROM
  • 32-bit wide 1GB DDR3 SDRAM
  • 32 MByte quad SPI Flash memory
  • Programmable clock generator
    • Transceiver clock (default 125 MHz)
  • Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
  • 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
  • 4 GTP/GTX (high-performance transceiver) lanes
    • GTP/GTX (high-performance transceiver) clock input
  • USB 2.0 high-speed ULPI transceiver
  • On-board high-efficiency DC-DC converters
    • 4 A x 1.0 V power rail
    • 3 A x 1.0 V power rail
    • 3 A x 1.2 V power rail
    • 3 5 A x 1.5 35 V power rail
    • 1.5 3 A x 1.8 V power rail
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • User LED
  • Evenly-spread supply pins for good signal integrity

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Hardware Revision History

DateRevision

Notes

Link to PCNDocumentation Link
2022-12-2105Third production release

Click to see PCN

TE0715-05
2016-06-2104Second production releaseClick to see PCNTE0715-04
-03First production release
TE0715-03
-02Prototypes
TE0715-02
-

01

Prototypes



Table 21: TE0715 module hardware revision history.

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Date

Revision

Contributors

Description

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Updated Key features: DCDC current rating
  • Added revision 5 in Hardware revision history
2021-06-21v.87John Hartfiel
  • Bugfix Link to PDF download
2018-07-06v.86John Hartfiel
  • Link to shop production list
  • Change normal Bank power note to important note

2017-11-14

v.85John Hartfiel
  • Replace B2B connector section
2017-09-10v.82Jan Kumann
  • Document template revision added.
  • Revised block diagram with new I2C part.
  • Power distribution diagram added.
  • Power-on sequence diagram added.
  • Sections rearranged, some missing ones added.
  • Weight section removed.
2017-06-07

v.64

Jan Kumann
  • Minor formatting.
2017-03-02

v.59

Thorsten Trenz
  • Corrected boot mode table.
2017-02-10

v.58

Thorsten Trenz
  • Corrected PLL initial delivery state.
2017-01-25
v.55


Jan Kumann
  • New block diagram.
2017-01-14

v.50

Jan Kumann
  • Product revision 04 images added.
  • Formatting changes and small corrections.
2016-11-15

v.45

Thorsten Trenz
  • Added B2B Connector section.
2016-10-18
v.40

Ali Naseri

  • Added table "power rails".
2016-06-28
v.38


Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann

  • New overall document layout with shorter table of contents.
  • Revision 01 PCB pictures replaced with the revision 03 ones.
  • Fixed link to Master Pin-out Table.
  • New default MIO mapping table design.
  • Revised Power-on section.
  • Added links to related Xilinx online documents.
  • Physical dimensions pictures revised.
  • Revision number picture with explanation added.
2016-04-27v.33

Thorsten Trenz, Emmanuel Vassilakis

  • Added table "Recommended Operating Conditions".
  • Storage Temperature edited.
2016-03-31v.10

Philipp Bernhardt, Antti Lukats

  • Initial version.

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