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A Microchip 24AA025E48 EEPROM (U19) is used on the TE0715. It is pre-programmed with has a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM). The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
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Bank | Voltage | TE0715-xx-15 | TE0715-xx-30 |
|---|---|---|---|
500 MIO0 | 3.3V | ||
501 MIO1 | 1.8V | ||
502 DDR | 1.5V | ||
0 Config | 3.3V | ||
13 HR | User | Max 3.3V | Max 3.3V |
34 HR/HP | User | Max 3.3V | Max 1.8V |
35 HR/HP | User | Max 3.3V | Max 1.8V |
PGOOD, EN1 and NOSEQ Pins
PGOOD
The PGOOD pin is an open drain output. It is forced low until all on-board power supplies are working properly.
NOSEQ
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System Controller I/O Pins
Special purpose pins used by TE0720 are also available on TE0715 they are connected to smaller System Controller CPLD and have different or no function in default configuration.
| Name | Note |
|---|---|
| EN1 | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset |
| PGOOD | Driven low by System Controller if power supply power fail detected |
| NOSEQ | No function |
| RESIN | Active low reset, gated to POR_B |
Bootmodes
By default the TE-0715 supports QSPI and SD bootmodes.
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MODE signal | bootmode |
|---|---|
high or open | SD Card |
low or ground | QSPI |
Clocking
Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 Mhz | U11 | PS_CLK | PS Subsystem main clock |
ETH PHY reference | 25 MHz | U9 | - | |
USB PHY reference | 52 MHz | U15 | - | |
PLL reference | 25 MHz | U18 | - | |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from base |
GT REFCLK1 | 125 Mhz | U10 Si5338 | U5/V5 | Default clock is 125 MHz |
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