Page History
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Bank | Type | JMx | IO Count | IO Voltage | Notes |
|---|---|---|---|---|---|
13 | HR | 1 | 48 | User | |
34 | HR/HP | 2 | 18 | User | 1.8V max with Z7030 |
35 | HR/HP | 2 | 50 | User | 1.8V max with Z7030 |
34 | HR/HP | 3 | 16 | User | 1.8V max with Z7030 |
500 | MIO | 1 | 8 | 3.3V | |
501 | MIO | 1 | 6 | 1.8V | |
112 | GT | 3 | 4 Lanesna | n/a | |
112 | GT CLK | 3 | one differential input | nan/a | AC coupling capacitors on base required |
For detailed information about the pinoutpin out, please refer to the Master Pinout Table.
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LED | Color | Connected to | Notes |
|---|---|---|---|
D2 | green | DONE | Inverted DONE, ON when FPGA not configured |
D3 | red | SC | Global status LED. |
D4 | green | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
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The reference clock input of the PHY is supplied from an onboard on board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
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PHY PIN | ZYNQ PS | ZYNQ PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | J3 | can be routed via PL to any free PL I/O pin in B2B connector |
| LED1 | - | K8 | can be routed via PL to any free PL I/O pin in B2B connector |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY Address is strapped to 0x00 alternate configuration is possible |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | -yes | on B2B |
| MDI | - | -yes | on B2B |
Note: LED1 is connected to PL via level-shifter implemented in system controller CPLD.
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The USB PHY USB3320 from Microchip is used on the TE0715. The ULPI interface is conected connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY is supplied from an onboard on board 52MHz oscillator (U15).
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PHY Pin | Zynq Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | 52MHz from onboard on board oscillator (U15) |
| REFSEL[0..2] | - | - | 000 GND, select 52MHz reference Clock |
| RESETB | MIO51 | - | Active low reset |
| CLKOUT | MIO36 | - | Connected to 1.8V selects reference clock operation mode |
| DP,DM | - | OTG_D_P, OTG_D_N | USB Data lines |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating |
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A Microchip 24AA025E48 EEPROM (U19) is used on the TE0715. It has contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM). The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
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Power Supplies
Vin | 3.3 V to 5.5 V | Typical 200mA200 mA, depending on customer design and connections |
Vin 3.3V | 3.3 V | Typical 50mA50 mA, depending on customer design and connections |
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| Name | Note |
|---|---|
| EN1 | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset |
| PGOOD | Driven low by System Controller if power supply power fail detected |
| NOSEQ | No function |
| RESIN | Active low reset, gated to POR_B |
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| JTAGEN | Low for normal operation |
Boot Modes
By default the TE-0715 supports QSPI and SD bootmodesboot modes.
Two bootmodes boot modes are controlled by the MODE signal on the board to board (B2B) connector:
MODE signal | bootmodeBoot Mode |
|---|---|
high or open | SD Card |
low or ground | QSPI |
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Parameter | Min on 7015 device | Max on 7015 device | Min on 7030 device | Max on 7030 device | Units | Notes |
|---|---|---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | -0.4 | 3.6 | V | |
| PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | -0.5 | 3.6 | V | |
PL IO Bank supply voltage for HP I/O banks (VCCO) | - | - | -0.5 | 2.0 | V | |
| I/O input voltage for HR I/O banks | -0.4 | VCCO+0.55 | -0.4 | VCCO+0.55 | V | |
| I/O input voltage for HP I/O banks | - | - | -0.55 | VCCO+0.55 | V | |
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards | -0.4 | 2.625 | -0.4 | 2.625 | V | |
| Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.26 | -0.5 | 1.26 | V | |
Voltage on JTAG pins | -0.4 | VCCO+0.55 | -0.4 | VCCO+0.55 | V | All dedicated pins (JTAG and configuration) are powered by VCCO_0 (refer to Xilinx UG865) |
Storage Temperature | -40 | +100 | -40 | +100 | C |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
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All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade moduelsmodules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
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