Page History

...

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to  to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

PL Peripherals

Both Ethernet PHY IC's are connected to PL pins in Bank 34, all PHY IC pins are connected to FPGA pins, there is no sharing of signals for the two PHY's.

...

Note the XADC capable pins are not routed differentially to the B2B connector. The performance and usability of the XADC must be evaluated.

Ethernet

There are two 100Mbit 100 MBit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25MHz 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.

...