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PS Peripherals (on-board)

Chip/InterfaceICPS7 Peripheral 
SPI FlashS25FL127SABMFV10QSPI016 MByte Flash
I2C EEPROM24xx64I2C08 KByte EEPROM
RTC I2CRV-3029I2C0 
RTC InterruptRV-3029GPIO - MIO0 
User LED GPIO - MIO7 

Mapping table for on-board IC to PS7 Peripherals

MIO PinMapped toPull up/downNotes
0GPIOUpRTC Interrupt
1QSPI0  
2QSPI0Down 
3QSPI0Down 
4QSPI0DownOverride to up on base for bootmode change
5QSPI0Up 
6QSPI0Down 
7GPIODownOn-board LED
8CAN1 TXDDownCAN transceiver
9CAN1 RXD CAN transceiver
10SPI1 MOSI  
11SPI1 MISO  
12SPI1 SCLK  
13SPI1 SS0  
14I2C0 SCLUpOn-board RTC, and EEPROM
15I2C0 SDAUpOn-board RTC, and EEPROM

Recommended Peripheral mapping for MIO Voltage bank 0.

PS7 UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to  PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

PL Peripherals

Both Ethernet PHY IC's are connected to PL pins in Bank 34, all PHY IC pins are connected to FPGA pins, there is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

 

PS and PL Banks

BankVCCIOB2B I/O PinsNotes
5003.3V0 
501USER J2.4 B2B36MIO1 VREF is connected to resistor divider to support HSTL18
13USER J1.39 B2B48Differential routing
333.3V33Single ended routing
343.3V0Ethernet PHY's
353.3V42Single ended routing
03.3V4JTAG, note 3 pins can be used as input only from PL Fabric

 

Clock sources

ICDescriptionFrequencyUsed as
U14MEMS Oscillator33.3333 MHzPS7 PLL clock
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzUsed by RTC, CLKOUT of RTC not connected

 

LED's

DesignatorColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenPL pin V18HighLVCMOS33

 

XADC Usage

XADC PinConnected toNotes
AD0B2B 
AD1B2B 
AD3B2B 
AD4B2B 
AD5B2B 
AD7PB2B 
AD7NGND 
AD8B2B 
AD9B2B 
AD10B2B 
AD12B2B 
AD13B2B 
AD14B2B 
AD15B2B 

XADC is used with internal reference option.

Note the XADC capable pins are not routed differentially to the B2B connector. The performance and usability of the XADC must be evaluated.

 

Ethernet

There are two 100Mbit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

 ETH1ETH2PullupNotes
CTREFJ3.57J3.25 Magnetics center tap voltage
TD+J3.58J3.28on-board 
TD-J3.56J3.26on-board 
RD+J3.52J3.22on-board 
RD-J3.50J3.20on-board 
LED1J3.55J3.23on-board 
LED2J3.53J3.21on-board 
LED3J3.51J3.19on-board 
POWERDOWN/INTL21R20on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_NM15R16on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

It is recommended to add IOB TRUE constraint for the MII Interface pins.

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

 

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Document Change History

DateRevisionAuthorsDescription
2015-05-10 Work in progress
 

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