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Old Version 8

changes.mady.by.user Thorsten Trenz

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New Version 9

changes.mady.by.user Ali Naseri

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NameNote
BOOTMODE 
CONFIGX 
JTAGENB 
RESIN 
M_TDOCPLD JTAG-Interface
M_TDICPLD JTAG-Interface
M_TCKCPLD JTAG-Interface
M_TMSCPLD JTAG-Interface
CLPD_GPIO0user GPIO
CLPD_GPIO1user GPIO
CLPD_GPIO2user GPIO
CLPD_GPIO3user GPIO
CLPD_GPIO4user GPIO
CLPD_GPIO5user GPIO

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Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

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DeviceICDesignatorI2C-AddressNotes
EEPROM24LC128-I/STU260x53??-
EEPROM24AA025E48T-I/OTU220x50MAC Address
EEPROM24AA025E48T-I/OTU240x51MAC Address
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57integrated in RTC
CLOCK GENERATORSI5338A-B-GMRU20x70Quad reference clock for GTX transceiver lanes
CPLDLCMXO2-1200HC-4TG100IU14user ??-

B2B I/O

Number of I/O's connected to the SoC's I/O bank and B2B connector

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