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  1. FPGA loads from address 0, Microblaze starts from BRAM with SREC Loader
  2. SREC Loader (customized part of it) checks some I/O pin to choose between update mode or normal mode
  3. In case of Update mode, SREC loader loads u-boot into external RAM and executes uboot
  4. In case of normal mode, warm boot is done by writes to HWICAP to start Application Bitstream

This process involves least amout of custom coding, the only custom code is small function that talks to HWICAP, and the "check" of update mode in the SREC Loader. All functions related to SPI Flash erasing and writing are done with u-boot.