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changes.mady.by.user Ali Naseri

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All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options .Contact us and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

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  • 2 x Gbps Ethernet PHY transceiver
  • 16-Bit wide 2 x 512 MByte DDR3 SDRAM
  • 32 MByte QSPI Flash Memory for configuration, operation and to store data
  • eMMC (4 GByte in standard configuration)
  • 2 x USB PHY transceiver
  • 16 GTX high-performance transceiver lanes
  • powerful switch-mode power supplies for all on-board voltages
  • large number of configurable I/Os is provided via rugged high-speed stacking strips

Block Diagramm

Image Added

Key Features

  • Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoM
  • Rugged for shock and high vibration
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte DDR3 SDRAM (2 x 16-Bit wide 512 MByte DDR3 SDRAM)
    • 32 MByte QSPI Flash memory
    • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
    • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64GByte)
  • 2 x MAC-Address EEPROMs
  • optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) or optional 2 x 32 64 MByte HyperFLASH
  • Temperature compensated RTC (real-time clock)
  • Si5338 PLL for GTX Transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver lanes
    • GT transceiver clock inputs
    • 254 FPGA I/O's (125 LVDS pairs)
  • On-board high-efficiency DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

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Signals, Interfaces and Pins

System

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Controller CPLD I/O Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782

NameNote
BOOTMODEuser configurable (CPLD)
CONFIGXuser configurable (CPLD)
JTAGENBJTAG operation
RESINSystem-reset
CLPD_GPIO0user GPIO
CLPD_GPIO1user GPIO
CLPD_GPIO2user GPIO
CLPD_GPIO3user GPIO
CLPD_GPIO4user GPIO
CLPD_GPIO5user GPIO

Small CPLD controls some functions of the SoM, this CPLD can be updated by the end user if support is designed on customer base.

Boot Modes

TE0782 supports primary boot from

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Note

JTAGENB pin in J3 should be kept low or grounded for normal operation.

Clocking

Silabs Multisynth PLL Si5338 can deliver GT reference clocks to all 4 GT Banks. Additionally a GT Reference clock can be generated on the base board for any of the 4 GT Banks. There is reference clock available on the TE0782 for Si5338, there is no need to supply a master reference clock from the base.

ClockFrequencyICZYNQ PS / PLNotes
PS
ClockFrequencyICFPGANotes
PS CLK33.3333 MHzU61BANK500, PS_CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHYs reference25 MHzU11- 
USB PHY reference52 MHzU7- 

PLL reference

25 MHz

U3

-

 

GT REFCLK1

-

B2B connector

BANK110, Pin AC7/AC8

Externally supplied from base

GT REFCLK4

-

B2B connector

BANK111, Pin U7/U8

Externally supplied from base

quad programmable clock (I2C)

SI5338A

userU2-

BANK110, Pin AA8/AA7

BANK109, Pin AF10/AF9

BANK111, Pin W8/W7

BANK112, Pin N8/N7

GT REFCLK0

GT REFCLK3

GT REFCLK5

GT REFCLK6

Processing System (PS) Peripherals

PeripheralICDesignatorZYNQ PS / PLMIONotes
QSPI FlashS25FL256SAGBHI20U38QSPI0MIO1...MIO6-
Ethernet0 ETH0 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U18ETH0; GPIO BANK35MIO16...MIO27, MIO52, MIO53-
Ethernet0 ETH0 10/100/1000 Mbps PHY Reset  GPIOMIO7ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
Ethernet1 ETH1 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U20GPIO BANK9, BANK35--PHY can be used with soft Ethernet MAC IP also
ETH1 Ethernet1 10/100/1000 Mbps PHY Reset  GPIO BANK35, Pin B15--
USB0USB3320C-EZKU4USB0MIO28...MIO39-
USB0 Reset  GPIOMIO0OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET
USB1USB3320C-EZKU8USB1MIO40...MIO51-
USB1 Reset  GPIOMIO0OTG_RESET33 (MIO0)  -> CPLD -> OTG_RESET
Clock PLLSi5338U2I2CBANK35, Pin L14/L15Low jitter phase locked loop
 e-MMC (embedded e-MMC)MTFC4GMVEA-4M IT  U15SDIO0MIO10...MIO15-
HyperFlash RAMS26KS512SDPBHI00xU9GPIO BANK35-

optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)

or optional 2 x 32 64 MByte HyperFLASH

HyperFlash RAMS26KS512SDPBHI00xU12GPIO BANK35-as above
EEPROM I2C24LC128-I/STU26GPIO BANK35, Pin L14/L15--
EEPROM I2C24AA025E48T-I/OTU22GPIO BANK35, Pin L14/L15-MAC Address
EEPROM I2C24AA025E48T-I/OTU24GPIO BANK35, Pin L14/L15-MAC Address
RTCISL12020MIRZU17GPIO BANK35, Pin L14/L15-Temperature compensated real time clock
RTC InterruptISL12020MIRZU17--RTC_INT -> CPLD

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MIOConfigured asB2BNotes
0OTG-RST33 -connected to CPLD
1QSPI0 -SPI Flash-CS
2QSPI0 -SPI Flash-DQ0
3QSPI0 -SPI Flash-DQ1
4QSPI0 -SPI Flash-DQ2
5QSPI0 -SPI Flash-DQ3
6QSPI0 -SPI Flash-SCK
7ETH1_RESET33 -connected to CPLD
8GPIO-connected to CPLD and Pull-Up 3.3V
9GPIO-connected to CPLD
10MMC-D0--
11MMC-CMD--
12MMC-CCLK--
13MMC-D1--
14MMC-D2--
15MMC-D3--
16..27ETH0-Ethernet RGMII PHY
28..39USB0-USB0 ULPI PHY
40...51USB1-USB1 ULPI PHY
52ETH0 MDC--
53ETH0 MDIO-
40...51USB1-USB1 ULPI PHY
52ETH0 MDC--
53ETH0 MDIO--

Pin Definitions

Pins named _vrn and _vrp are connected to ZYNQ PL HP Bank special purpose pins VRN/VRP. If needed they can be connected to DCI calibration resistors on the base. If not, then those pins can be used as general purpose I/O.

Bank B35 has 100 ohm DCI calibration resistors installed on TE0782, it is also possible to "borrow" the DCI calibration from B35 for banks B34, and B33. For detailed usage of the DCI check Xilinx documentation.

I2C Interface

The on-board I2C components are connected to BANK35, Pin L15 (I2C_SDA) and to BANK35, Pin L14 (I2C_SCL).

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LED's

D1 - Onboard RED LED

Frequency of LED-Toggling [1/2.6sec]Status
1Power problem
2MGT Power problem
3Reset from mainboard
4FPGA not programmed

This function depend on the CPLD revision.

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ETH1 PHY connection:

PHY PINZYNQ PS / PLSystem Controller CPLDNotes
MDC/MDIOMIO52, MIO53--
LED0BANK35, Pin B12--
LED1BANK35, Pin C12--
InterruptBANK35, Pin A15--
CONFIGBANK35, Pin F14--
RESETn-Pin 53ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
RGMIIMIO16..MIO27 -
MDI--on B2B J2 connector

ETH2 PHY connection:

PHY PINZYNQ PS / PLSystem Controller CPLDNotes
MDC/MDIOBANK35, Pin C17/B17--
LED0BANK35, Pin K15--
LED1BANK35, Pin B16--
InterruptBANK35, Pin A17--
CONFIGBANK35, Pin E15-Pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnBANK35, Pin B15--
RGMIIBANK9--
MDI-

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on B2B J2 connector

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USB0 PHY connection:

PHY PinZynq PinZYNQ PS / PLCPLDB2B Name (J2)Notes
ULPIMIO28..39--Zynq USB0 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
RESETBMIO0OTG_RESET33-OTG_RESET33 -> CPLD -> OTG_RESET
CLKOUTMIO36--Connected to 1.8V selects reference clock operation mode
DP,DM--USB1_D_P, USB1_D_NUSB Data lines
CPEN--VBUS1_V_ENExternal USB power switch active high enable signal
VBUS--USB1_VBUSConnect to USB VBUS via a series resistor. Check reference schematic
ID--OTG1_IDFor an A-Device connect to ground, for a B-Device left floating

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USB1 PHY connection:

PHY PinZynq PinZYNQ PS / PLCPLDB2B Name (J2)Notes
ULPIMIO40..51--Zynq USB1 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
RESETBMIO0OTG_RESET33-OTG_RESET33 -> CPLD -> OTG_RESET
CLKOUTMIO48--Connected to 1.8V selects reference clock operation mode
DP,DM--USB2_D_P, USB2_D_NUSB Data lines
CPEN--VBUS2_V_ENExternal USB power switch active high enable signal
VBUS--USB2_VBUSConnect to USB VBUS via a series resistor. Check reference schematic
ID--OTG2_IDFor an A-Device connect to ground, for a B-Device left floating

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Two Microchip 24AA025E48 EEPROMs (U22 and U24) are used on the TE0782. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. Those are accessible by the I2C slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .

Power

For startup, a power supply with minimum current capability of 3A is recommended.

VIN and 3.3VIN can be connected to the same source (3.3 V).

Power Supplies

Input Power Supply

Power RailNet nameVoltageI maxNotes
Standby powerC3.3V3.3V100mASystem Control CPLD Power
Main powerVIN12VTBDMain power for all on-board DCDC Regulators

Supply Voltage

Voltage Range

note

Vin

3.3 V to 5.5 V

Typical 200 mA, depending on customer design and connections

Vin 3.3V3.3 VTypical 50 mA, depending on customer design and connections

Bank Voltages

BankVoltagemax. Valuenote
03,3 V-FPGA Configuration
5021,5 V-DDR3-RAM Port
109 / 110 / 111 / 1121,2 V-FPGA MGT
500 / 5013,3 V-MIO Banks
91,8 V-ETH2 RGMII
10user3,3 VB2B name: VCCIO_10
11user3,3 VB2B name: VCCIO_11
12user3,3 VB2B name: VCCIO_12
13user3,3 VB2B name: VCCIO_13
33user3,3 VB2B name: VCCIO_33
34user3,3 VB2B name: VCCIO_34
351,8 V-Hyper-RAM, Ethernet, I2C

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ParameterMinMaxUnitsNotesReference document
Vin supply voltage2.55.5V  
Vin33 supply voltage3.1353.465V  
VBat supply voltage2.75.5V  
PL IO Bank supply voltage for HR I/O banks (VCCO)1.143.465V Xilinx document DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheetXilinx document DS191 and DS187
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 

Physical Dimensions

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Please download the assembly diagram for exact values.

  • Module size: 85 mm × 85 mm for exact numbers.

  • Mating height with standard connectors: 8mm5 mm

  • PCB thickness: 1.6mmHighest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.,7 mm

All dimensions are shown in mm.Image RemovedImage Removed

 

Image Added

Weigt

Part

60 g

Plain module

Temperature Ranges

Commercial grade modules

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All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

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Weigt

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Part

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g

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Plain module

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Document Change History

daterevisionauthorsdescription
2016-06-27v10initial release

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