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The Trenz Electronic TE0703 Carrier Board is a base-board for 4x5 4 x 5 SoMs, which exposes the MIO- and the PS/PL-pins of the SoM to accessible connectors and provides a whole range of on-board-components to test and evaluate Trenz Electronic 4x5 4 x 5 SoMs.

See page "4 x 5 cm carriers" to get information about the SoM's supported by the TE0703 Carrier Board.

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  • On Board:
    • USB JTAG and UART interface (FTDI FT2232H), compatible with Xilinx tools (also with many other tools)
    • SDIO port expander with voltage-level translation
    • 4 x User LEDs
      • D1 and D2 are connected to the carrier controller, their function depends on the firmware
      • D3 and D4 are connected to the 4 x 5 module B2B connector pins, and are directly controlled by the module
    • 1 x User push button
      • Connected to "intelligent Carrier Controller (iCC)" and can be used as module reset button. Other usage possible, actual function depend on the code loaded into iCC.
    • 4A high efficiency power SoC 6 A DC-DC step-down converter with integrated inductor (Enpirion EN6347) inductor for 3.3V power supply
    • 4 User DIP switches
      • Enable/disable update of the "intelligent Carrier Controller"
      • MIO0 (readable signal by iCC and module)
      • 2 "mode" bits
  • Interface:
    • Trenz 4 x 5 module socket (3 x Samtec LSHM series connectors) 
    • Micro SD card connector - Zynq SDIO0 bootable SD port
    • 2 x VG96 backplane connectors (mounting holes and solder pads)
    • Mini USB connector (USB JTAG and UART interface)
    • RJ45 GbE connector
    • USB host connector
  • Power:
    • Barrel jack for 5V power supply input
  • Dimension:
    • 100 mm x 64.5 mm

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Scroll Title
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titleTExxxx TE0703 block diagram


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Main Components

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titleTExxxx main components


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  1. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
  2. Samtec Razor Beam™ LSHM-150 B2B connector, JB2
  3. Samtec Razor Beam™ LSHM-130 B2B connector, JB3
  4. Micro SD card socket with detect switch, J3
  5. LED indicators D1 and D2
  6. Mini-USB type B connector, J4
  7. LED indicators D3 and D4
  8. Configuration DIP switches, S2 (see table under "DIP switches" section)
  9. User push button (Reset), S1
  10. External connector (VG96) placeholder, J1
  11. External connector (VG96) placeholder, J2
  12. VCCIO voltage selection jumper block, J5, J8, J9 and J10 (see "Power and Power-On Sequence" section)
  13. Trxcom 1000Base-T Gigabit RJ45 Magjack, J14 with 4 integrated LEDs
  14. USB type A receptacle, J6 (optional micro USB 2.0 type A/B receptacle available, J12)
  15. 5V power connector jack, J13
  16. SD IO voltage (VCCA) selection jumper J11

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Scroll Title
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titleInitial delivery state DIP switches

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SwitchPositionDescription
S2-1ONMode control MC1.
S2-2ONFPGA access on module (need also S2-3 ON)

S2-3

ONFPGA access on module (need also S2-2 ON)
S2-4OFFBoot mode set to QSPI.


Different delivery configurations are available upon request.

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Scroll Title
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titleBoot process.

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Control signal

Switch /Button/ LED /Pin

Signal Schematic NamesConnecte toFunctionalityNotes
Module  JTAG selectDip switche S2-2CM0SC CPLD pin 75

ON: Module JTAG access ( if S2-3 ON)

OFF: Module CPLD JTAG access ( if S2-3 ON)

TE0703 CPLD - CC703S#CC703S-JTAG
Module JTAG selectSC CPLD pin 104PROGMODEB2B JB1 pin 90Enable B2B Module JTAG access to CPLD for Firmware updateselect: Module CPLD high or SoC/FPGA JTAG low ; via CPLD firmware linked to CM0TE0703 CPLD - CC703S#CC703S-JTAG
Carrier CPLD JTAG enable

Dip switch S2-3

JTAGEN

SC CPLD pin 120

ON: SoM JTAG access

OFF: Carrier SC CPLD JTAG access

TE0703 CPLD - CC703S#CC703S-JTAG
Select boot modeDip switche S2-4MIO0

SC CPLD pin 94

and B2B JB1 pin 88

ON: Boot from SD Card

OFF: Boot from QSPI flash on module

TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode is also module dependent
Select boot modeSC CPLD pin 83

MODE

B2B JB1 pin 31SD-CARD (Zynq) or QSPI-Flash; via CPLD firmware linked to MIO0TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode is also module dependent
ResetS1S1SC CPLD pin114global resetTE0703 CPLD - CC703S#CC703S-Reset
ResetSC CPLD pin 119RESINB2B JB2 pin 17via CPLD firmware linked to S1TE0703 CPLD - CC703S#CC703S-Reset
Moduel enableSC CPLD pin 81

EN1

B2B JB1 pin 27Module power enablepulled up by CPLD
Disable CPLD power ManagementSC CPLD pin 78NOSEQB2B JB1 pin 8Disable CPLD power managementpulled up by CPLD
Disable Card detect pinDip switche S2-1

CM1

SC CPLD pin 76

ON: Force CD Pin to module to GND

OFF: Set CD Pin to module to SD CD Pin

TE0703 CPLD - CC703S#CC703S-SD
SD Card detectSD Card Socket J3 pin 9SD_CDSC CPLD pin93Low if Card detectedTE0703 CPLD - CC703S#CC703S-SD
SD SelectorSC CPLD pin 113SD_SELU2 pin 24FIXed to GND: Select SD Card  (CPLD SD port not used)TE0703 CPLD - CC703S not used


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Micro SD card socket is connected to the B2B connector through a Texas Instruments TXS02612 SDIO port expander for voltage translation. The Micro SD card has 3.3V signal voltage level while most 4x5 4 x 5 modules use 1.8V for the SD card interface.

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titleJTAG pins connection

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Signal

B2B Connector Pin

Note
M_TCKU5-131CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, dependent on Dip switches linked to Module JTAG Port on JB2.
M_TDIU5-136
M_TDOU5-137
M_TMSU5-130
FT_B_TXU5-139CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, linked to Module primary UART on JB1.
FT_B_RXU5-138
ADBUS7U5-142CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, currently not used.
ADBUS4U5-143
ACBUS4U5-141
ACBUS5

U5-140

BDBUS2U5-133
BDBUS3U5-132
BDBUS4U5-128
BDBUS5U5-127
BDBUS6U5-126
BDBUS7U5-125
BCBUS0U5-122
BCBUS1U5-121

LEDs

There are four on-board LEDs. D3 and D4 are  connected to the B2B connector JB2 pins FLED1 and FLED2 respectively and can be read by CPLD firmware.


CPLD

TE0703-06 has a Lattice LCMXO2-1200HC as a system controller. for further function description see Firmware TE0703 CPLD - CC703S#CC703S,

SD IO Levelshifter

SD IO levelshifter (U2) is used in congntion with jumper J11 to select the correct SD IO interface voltage of the SoM. 

I2C Repeater

For power sequence reasons the I2C bus is routed via a repater (U7) to to ensure no IOs of the SoM are driven before M3.3VOUT is up.

LEDs

There are four on-board LEDs. D3 and D4 are  connected to the B2B connector JB2 pins FLED1 and FLED2 respectively and can be read by CPLD firmware. See TE0703 CPLD - CC703S#CC703S-LED.

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titleOn-board LEDs

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LEDColorSignalConnected toDescription
D1RedULED1U5-117FTDI UART receive activity.
D2GreenULED2U5-115FTDI UART transmit activity.
D3RedFLED1JB2-99Module LED, CPLD can read status via signal FL_0 connected via 10K.
D4GreenFLED2JB2-90Module LED, CPLD can read status via signal FL_1 connected via 10K.


DIP switches

DIP switch settings are CPLD Firmware dependent, default firmware:

Scroll Title
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titleDip-Switches

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SwitchONOFFNotes
S2-1Set PGOOD pin to low ('0') / Force CD
Pin
pin to module to
GNDset CD Pin
high impedance ('Z')Set PGOOD pin to high ('1') / Set CD pin to module to SD_CD
Pin
pinTE0703 CPLD - CC703S#CC703S-BootMode /  TE0703 CPLD - CC703S#CC703S-SD
S2-2Module FPGA  JTAG access ( if S2-3 ON)Module CPLD JTAG access ( if S2-3 ON)
 
TE0703 CPLD - CC703S#CC703S-JTAG
S2-3Module FPGA/CPLD  JTAG access (
 
depends on S2-
3
2)Carrier CPLD  JTAG access
 
TE0703 CPLD - CC703S#CC703S-JTAG
S2-4
 Boot
Boot from SD Card (
set Pin
Set pin to GND)Boot from QSPI flash on module (
set Pin
Set pin to VDD)
 

TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode

is also  module depends

also depends on module.


Mode status is displayed on TE0703 LEDs, see TE0703 CPLD - CC703S#CC703S-LED.

Jumper

TE0703-06 has 5 Voltage selection jumpers. Select 1.8V or 3.3V in accordenc of the attached module capabilities and your needs. Refer to the 4x5 4 x 5 Module Integration Guide for VCCIO voltages options.

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titleJumpers

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Power RailJumper

1.8V

3.3VNotes
VCCIOAJ51-22-3-
VCCIOBJ81-22-3-
VCCIOCJ91-22-3-
VCCIODJ101-22-3-
VCCAJ111-22-3SD IO level shifter
Voltage Selection
voltage selection (module side), compare with TRM of attached Module



Scroll Title
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titleTExxxx main componentsTE0703 Jumper Settings


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Note

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

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Scroll Title
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titlePower Consumption

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Power Input PinMax Current
VIN (power connector jack J13)4A


Typical power consumption for TE0703-05 + TE0715-01 module with SD micro card inserted, Ethernet connected and link up, system booted into Linux prompt and idling is 5V / 0.55A.

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titleModule power rails.

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Power Rail Name

Connector-Pin

DirectionNotes
5VINJ13-1in5 V power input
VIN- -5 V power input after protection
3.3VJB1-2, 4, 6, 14, 16outGeneratet from VIN by DCDC U3,  constant 3.3V rail
M1.8VOUTJB1-40 in1.8V from Module.
M3.3VOUTJB2-9, 11in3.3V from Module.
VCCIOAJB1-10, 12outUse jumper J5  to source by M1.8VOUT or M3.3VOUT.
VCCIOBJB2-2 ,4outUse jumper J8  to source by M1.8VOUT or M3.3VOUT.
VCCIOCJB2-6outUse jumper J9  to source by M1.8VOUT or M3.3VOUT.

VCCIOD

JB2-8, 10out

JB2-8, 10outUse jumper J10  to source by M1.8VOUT or M3.3VOUT.
VCCA--SD IO leveshifter voltge on Module side. Use jumper J11 Use jumper J10  to source by M1.8VOUT or M3.3VOUT.
VCCJTAGJB2-92inJTAG reference voltage
USB-VBUS_RJ6-1 (J12-1)out5V USB, derived from VIN by power switch U1


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Scroll Title
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titlePhysical Dimension


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Hardware Revision History

voltage selection jumper20161122

Date

Revision

Notes

PCN

Documents
2023-09-0407

See Revision changes.



2019-09-0206

Added SD IO

voltage selection jumper

Further changes  see PCN.

PCN-20190104TE0703

2016-09-07

05

Added VCCIO Jumpers

PCN-20161122

TE0703-05

-

04

Corrected FTDI EEPROM connection

-

TE0703-04

-

03

Added VCCIO strapping resistors

-


-

02

First series boards

-


-

01

Prototypes

-


Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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Document Change History

updating

Date

Revision

Contributors

Description

Page info
infoTypeModified date
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typeFlat

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  • updated to REV07
2022-09-23v.44Mohsen Chamanbaz
  • Changing in the dip-switches table because of updating of CPLD firmware (CPLD Firmware REV03)
2019-10-07v.43Martin Rohrmüller
  • updated to REV06
  • updated to TRM style 2.12

2018-06-13


v.29

Ali Naseri
  • updating operating conditions
2017-02-07v.28John Hartfiel
  • Add DIP setting description
2017-11-09v.26John Hartfiel
  • add B2B connector section
2017-02-21

v.19


Jan Kumann
  • New block diagram.
2017-02-02

v.16

Jan Kumann
  • New board image with silk screen pin markings for VG96 connectors J1 and J2.
2016-12-22

v.14

Jan Kumann
  • Block diagram added.
2016-12-08
v.10

Jan Kumann

  • Document structure revised.
2016-12-05

v.5

John Hartfiel
  • Corrected Boot Mode table.
2016-09-06

v.1

Jan Kumann, John Hartfiel

  • Initial document.

Disclaimer

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IN:Legal Notices
IN:Legal Notices

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