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  • Xilinx Virtex-7 FPGA module XC7VX330T-2FFG1157C (commercial temperature range)
  • PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
  • FMC High Pin Count (HPC) connector
  • 8 FPGA MGT lanes available on PCIe interface
  • DDR3 SO-DIMM SDRAM socket
  • 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
    • FPGA
    • JTAG port (SPI indirect, bus width x4)
  • External clock input via SMA coaxial connector
  • 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
  • FPGA configuration through:
    • JTAG connector
    • Quad SPI Flash memory
  • Programmable quad clock generator
  • TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner
  • On-board high-efficiency DC-DC converters
  • Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
  • System management and power sequencing
  • AES bit-stream encryption
  • eFUSE bit-stream encryption

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Block Diagram


Figure 1TEC0330-03 Block Diagramblock diagram.

Main Components

 

Figure 2: FPGA board TEC0330-03.

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The I/O signals are routed from the FPGA I/O banks to the FMC connector as LVDS pairs:

FPGA BankI/O SignalsLVDS pairsBank Voltage (VCCO)
Notes
Bank 1992461.8V-
Bank 394221VIO_B_FMC

Bank voltage VIO_B_FMC must be supplied by FMC connector pins J2-J39, J2-K40.

Bank's VREF_B_M2C signal is routed to the FMC connector pin J2-K1 (external reference voltage).

Bank 3734171.8VBank's VREF_A_M2C signal is routed to the FMC connector pin J2-H1 (external reference voltage).
Bank 3834171.8VBank's VREF_A_M2C signal is routed to the FMC connector pin J2-H1 (external reference voltage).

Table 2: Overview of the FPGA I/O bank signals routed to the FMC.

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There are also 10 high-speed MGT lanes (Xilinx GTH transceivers) from different FPGA MGT banks routed to the FMC connector.The MGT banks have also clock input pins which are exposed to the FMC connector. Following MGT lanes are available on the FMC connector:

FPGA BankI/O signalsSignalsLVDS pairsPairsMGT lanesLanesMGT Bank's reference clock (LVDS pair)Reference Clock
1161085421 clock-signal from clock synthesizer U9 to bank's pins T6/T5.
117201610842 clock-signals from clock FMC connector GBTCLK0_M2C and GBTCLK1_M2C (pins J2-D4/J2-D5 and J2-B20/J2-B21) to bank's pins M6/M5 and P6/P5.
11820161084

1 reference clock from clock synthesizer U9 to bank's pins F6/F5

1 reference clock from  programmable quad clock generator U13 to bank's pins H6/H5.

Table 3: Overview of MGT banks lanes routed to the FMC connector.

 

The FMC connector has also two reference clock input pairs (LVDS) routed to the FPGA MGT bank 117, see also section MGT lanes.

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The FMC connector provides JTAG and There are also JTAG, I2C interfaces to the interface and power good control signals routed between FMC connector and System Controller CPLD:

Interface I/O
signals
Signals
Schematic
name
Name / FMC
pin
PinConnected toNotes
JTAG5

FMC_TRST, pin D34

FMC_TCK, pin D29

FMC_TMS, pin D33

FMC_TDI, pin D30

FMC_TDO, pin D31

SC CPLD, bank 2VCCIO: 3V3PCI.
I2C2

FMC_SCL, pin C30

FMC_SDA, pin C31

SC CPLD, bank 2

VCCIO: 3V3PCI.

I2C-lines 3V3PCI pulled-up.

Control lines3

FMC_PRSNT_M2C_L, pin H2

FMC_PG_C2M, pin D1 (3V3FMC pull-up)

FMC_PG_M2C, pin F1 (3V3FMC pull-up)

SC CPLD, bank 1

PG - Power Good signal.

C2M - carrier to mezzanine module.

M2C - mezzanine module to carrier.

Internal System Controller CPLD signal assignment:

FEX_0_N <= FMC_PG_M2C

FMC_PG_C2M <= FMC_PRSNT_M2C_L

Table 4:  FMC connector pin-outs of available interfaces to the System Controller CPLD.

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FPGA bank 17 and 18 clock inputs from FMC connector:

Schematic nameName
FMC connector pinsConnector PinsFPGA bankBankFPGA pinsPins
CLK0_P, CLK0_NH4, H517R28, R29
CLK1_P, CLK1_NG2, G317P29, P30
CLK2_P, CLK2_NK4, K518G31, G31
CLK3_P, CLK3_NJ2, J318H29, H30

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Several VCCIO voltages are available on the FMC connector for FPGA I/O banks:

Schematic nameNameMax currentCurrentFMC connector pinsConnector PinsNotes
12V1AC35/, C37Externally supplied 12V
3V3PCI20mAD32Supplied by the PCIe interface
3V3FMC3AD36/, D38/, D40/, C39Supplied by DC-DC converter U15
VIO_B_FMCExternal supplyJ39/, K40Externally supplied VCCO to HB FPGA bank 39
FMC_VADJ4AH40/, G39/, F40/, E39Fixed to 1.8V, supplied by DC-DC converter U7

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Table 10: MGT banks reference clock sources.

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JTAG Interfaces

There are three JTAG interfaces available on the TEC0330 board:

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Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA module and to display its programming state.

SC CPLD
bank
BankCPLD
bank
Bank's VCCIO
03V3PCI
13V3PCI
23V3PCI
31V8

Table 12: VCCIO voltages of CPLD banks.

 

Following table describes the interfaces and functionalities of the System Controller CPLD , which are not described elsewhere in this TRM:

CPLD
functionality
FunctionalityInterfaceDesignated CPLD
pins
PinsConnected to
Notes
I2C interface between on-board peripherals and FPGAI2C
  • FPGA_IIC_SDA, pin 24
  • FPGA_IIC_SCL, pin 25
  • FPGA_IIC_OE, pin 19
  • FPGA bank 16, pin V29
  • FPGA bank 16, pin W29
  • FPGA bank 16, pin W26

VCCIO: 1V8, all with pull-up to 1V8.

Following devices and connectors are linked to the FPGA_IIC I2C interface:

  • DC-DC converter U3 and U4 (LT LTM4676)
  • Programmable quad clock generator U13
  • FMC connector J2
  • PCIe connector J1

Note: FPGA_IIC_OE must kept high for I2C operation.

For I2C slave device addresses refer to the component datasheets.

User I/Os

External LVDS pairs

10 I/Os

5 x

differential signaling

LVDS pairs

  • EX0_P ... EX4_P
  • EX0_N ... EX4_N
  • IDC header J7

Can also be used for single-ended signaling.

User I/Os

Internal LVDS pairs

13 I/Os

6 x

differential signaling

LVDS pairs

  • FEX0_P ... FEX5_P
  • FEX0_N ... FEX5_N
  • FEX_DIR (single-ended I/O)
  • FPGA bank 18

VCCIO: 1V8

Can also be used for single-ended signaling.

FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK).

Internal signal assignment:

FEX_DIR <= FMC_PRSNT_M2C_L

FPGA programming control and state2 I/Os
  • DONE, pin 7
  • PROGRAM_B, pin 8
  • FPGA bank 0, pin V8
  • FPGA bank 0, pin U8
VCCIO: 1V8
I2C interface to programmable quad clock generator
I²C
I2C
  • PLL_SCL, pin 14
  • PLL_SDA, pin 15
  • U13, pin 12
  • U13, pin 19

VCCIO: 1V8

Only PLL_SDA has 1V8 pull-up.

Fan PWM control J42 I/Os
  • F1SENSE, pin 99
  • F1PWM, pin 98
  • J4-3 (active low)
  • J4-4

Internal signal assignment:

  • FEX_5_P <= F1SENSE
  • FEX_5_N => F1PWM
Button S21 I/O
  • BUTTON, pin 77
  • Switch S2
Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration.
LED11 I/O
  • LED1, pin 76
  • LED D1 (green)

Fast blinking, when FPGA is not programmed.

Internal signal assignment:

  • LED1 <= Button S2 or FEX0_P

PCIe control line RESET_B

1 I/O
  • PCIE_RSTB, pin 37
PCIe connector
  • J1-A11
(33R serial resistor)

Internal

Internal

signal assignment:

  • FEX_4_N <= PCIE_RSTB

Control

Interface

interface to clock synthesizer U9 (TI LMK04828B)

SPI (3 I/Os),

4 I/Os

  • CLK_SYNTH_SDIO, pin 75
  • CLK_SYNTH_SCK, pin 74
  • CLK_SYNTH_RESET, pin 54
  • CLK_SYNTH_CS, pin 53
  • CLK_SYNTH_SYNC, pin 52
  • LMK_STAT0, pin 62
  • LMK_STAT1, pin 63
  • U9, pin 20
  • U9, pin 19
  • U9, pin 5
  • U9, pin 18
  • U9, pin 6
  • U9, pin 31
  • U9, pin 48

Pull up to 3V3PCI.

  • Internal signal assignment:
  • LMK_SCK <= FEX_1_P
  • LMK_SDIO <= FEX_1_N
  • LMK_CS <= FEX_3_P
  • LMK_SYNC <= EX_3_N
  • LMK_RESET <= FEX_4_P
  • FEX_2_P => LMK_SDIO (FEX_2_N must be 0)
  • LMK_STAT0 and LMK_STAT1 signals are not used.
Control Interface to DC-DC converters U3 and U4 (both
LT
LTM4676)

I2C (2 I/Os),

2 I/Os

  • LTM_SCL, pin 67
  • LTM_SDA, pin 66
  • LTM1_ALERT, pin 65
  • LTM2_ALERT, pin 64
  • U4, pin E6 and U3, pin E6
  • U4, pin D6 and U3, pin D6
  • U4, pin E5
  • U3, pin E5

3V3 pull-ups.

LTM I2C interface is also accessible trough header J10.

LTM1_

Alert

ALERT and LTM2_ALERT signals are not used.

Power-on sequence and monitoring6 I/Os
  • EN_1V8, pin 58
  • PG_1V8, pin 59
  • EN_FMC_VADJ, pin 60
  • PG_FMC_VADJ, pin 61
  • EN_3V3, pin 51
  • PG_3V3, pin 57
  • U20, pin 27
  • U20, pin 28
  • U7, pin 27
  • U7, pin 28
  • U15, pin 27
  • U15, pin 28

Sequence of the supply voltages depend on the System Controller CPLD firmware.

EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.

PG signals will not be evaluated.

Table 13: Overview of the System Controller CPLD functions.

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The TEC0330 board supports additional DDR3 SO-DIMM via 204-pin SO-DIMM socked socket U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.

The reference clock signal for the DDR3 interface is generated by the quad programmable reference clock generator U13 and is applied to the FPGA bank 35.

There is also a I2C interface between the System Controller CPLD and the DDR3 SDRAM memory:

Interface signals schematic nameSignals Schematic NameSystem Controller CPLD pinPinDDR3 memory interface pinMemory Interface Pin
DDR3_SDABank 2, pin 48Pin 200 (3V3PCI pull-up)
DDR3_SCLBank 2, pin 49Pin 202 (3V3PCI pull-up)

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Clock SourceSchematic NameFrequencyClock destinationDestination
SMA coaxial connector, J3

CLK_SYNTH_CLKIN0_P,

CLK_SYNTH_CLKIN0_N (GND)

UserClock synthesizer U9, pins 37/38
RAKON P5146LF oscillator, U11-10.0 MHzClock synthesizer U9, pins 43/44
SiTime SiT8208 oscillator, U14CLK_25MHz25.0 MHzProgrammable quad clock generator U13, pin 3
FMC connector J2, pins H4/H5

CLK0_P, CLK0_N

UserFPGA bank 17, pins R28/R29
FMC connector J2, pins G2/G3CLK1_P, CLK1_NUserFPGA bank 17, pins P29/P30
FMC connector J2, pins K4/K5CLK2_P, CLK2_NUserFPGA bank 18, pins G30/G31
FMC connector J2, pins J2/J3CLK3_P, CLK3_NUserFPGA bank 18, pins H29/H30
FMC connector J2, pins D4/D5

GBTCLK0_M2C_P,

GBTCLK0_M2C_N

UserFPGA bank 117, pins M6/M5
FMC connector J2, pins B20/B21

GBTCLK1_M2C_P,

GBTCLK1_M2C_N

UserFPGA bank 117, pins P6/P5
PCIe interface J1, pins A13/A14

PCIE_CLK_P,

PCIE_CLK_N

100 MHz

(PCIe spec.)

FPGA bank 115, pins AD6/AD5

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There is a Silicon Labs I2C programmable quad clock generator Si5338A (U13) on-board. It's output frequencies can be programmed by using the are programmable via FPGA I2C -bus with address 0x70interface using slave device address 0x70 (corresponding I2C logic has to be implemented in FPGA design).

A 25 MHz (U14) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA module to utilize I²C-bus correctlythe output clocks.

Si5338A (U13) input InputSignal schematic nameSchematic NameNotes

IN1/IN2

CLKIN_5338_C_P, CLKIN_5338_C_N

Reference clock signal from clock synthesizer U9 (100 nF decoupling capacitors and 100Ω termination resistor).

IN3

Reference clock oscillator input, SiTime  SiT8208AI (U14).

25.0 MHz fixed frequency.

IN4/IN6

Connected to the GND.LSB (pin 'IN4') of the default I²C-adress 0x70 is zero.

IN5

Not connected

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Si5338A (U13) outputOutput
Signal schematic nameSchematic NameNotes

CLK0 A/B

DDR3_CLK_P, DDR3_CLK_N

DDR3-RAM reference clock signal to FPGA bank 35.

CLK1 A/B

MGTCLK_5338_C_P,

MGTCLK_5338_C_N

Reference clock signal to FPGA bank 115 MGT (100 nF decoupling capacitors and 100Ω termination resistor).

CLK2 A/B

LMK_CLK_P, LMK_CLK_N

Input clock signal to clock synthesizer U9 (100 nF decoupling capacitors).

CLK3 A/B

MGTCLK2_5338_C_P,

MGTCLK2_5338_C_N

Reference clock signal to FPGA bank 118 MGT (100 nF decoupling capacitors and 100Ω termination resistor).

Table 16: I/O pin description of programmable clock generator Si5338A.

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LMK04828B (U9) inputsignal schematic nameNote
Status_LD1, Status_LD2LMK_STAT0, LMK_STAT1Connected to System Controller CPLD, not implemented in current CPLD firmware.

SPI interface and control lines

see section 'System controller CPLD'The clock synthesizer can be controlled and programmed by IC is accessible to the FPGA module via the SPI interface and control lines, which are by-passed routed through the System Controller CPLD.
CLKin0, CLKin0*

CLK_SYNTH_CLKIN0_P,

CLK_SYNTH_CLKIN0_N

Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF.

CLKin0 to connected to GND via serial decoupling capacitor 100nF. 

CLKin1, CLKin1*

CLK_SYNTH_CLKIN1_P,

CLK_SYNTH_CLKIN1_N

Input reference clock signal from programmable quad clock generator Si5338A (U13) via serial decoupling capacitor 100nF.
OSCin, OSCin*-Signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz.
LMK04828B (U9) outputsignal schematic nameNote
DCLKout0, DCLKout0*

CLK_SYNTH_DCLKOUT0_P,

CLK_SYNTH_DCLKOUT0_N

Reference clock signal to FPGA bank 15 pins AD29/AE29.
SDCLKout1, SDCLKout1*

CLK_SYNTH_SDCLKOUT1_P,

CLK_SYNTH_SDCLKOUT1_N

Reference clock signal to FPGA bank 15 pins AE31/AF31.
DCLKout2, DCLKout2*

CLKIN_5338_P,

CLKIN_5338_N

Reference clock signal to programmable quad clock generator Si5338A (U13) (100 nF decoupling capacitors and 100Ω termination resistor).

DCLKout4, DCLKout4*

CLK_SYNTH_DCLKOUT4_P,

CLK_SYNTH_DCLKOUT4_N

Reference clock signal to FPGA MGT bank 115 MGT, pins T6/T5.
SDCLKout7, SDCLKout7*

CLK_SYNTH_SDCLKOUT7_P,

CLK_SYNTH_SDCLKOUT7_N

Reference clock signal to FPGA MGT bank 118 MGT, pins F6/F5.
OSCout0, OSCout0*

CLK_SYNTH_CLKIN2_P,

CLK_SYNTH_CLKIN2_N

Reference clock signal to FPGA bank 18, pins J30/J31 (100 nF decoupling capacitors).

Table 17: Pin description of clock synthesizer TI LMK04828B.

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Table 18: Typical power consumption.

TBD  - To Be Determined.

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Power-On Sequence

The on-board voltages of the TEC0330 FPGA board will be are powered up in order of a determined predefined sequence after the external voltages 12V on connector J5 and 3V3PCI on connector J1 are become available.

Core voltages and main supply voltages have to reach stable state and their "Power Good" - signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.

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BankSchematic NameVoltageRangeNoteNotes
01V81.8VHP: 1.2V to 1.8VConfig bank (fixed to 1.8V) / JTAG interface.
141V81.8VHP: 1.2V to 1.8VQSPI flash memory interface.
151V81.8VHP: 1.2V to 1.8VReference clock input.
161V81.8VHP: 1.2V to 1.8VI2C interface of FPGA.
171V81.8VHP: 1.2V to 1.8VReference clock input.
181V81.8VHP: 1.2V to 1.8VReference clock input / I/O's to CPLD.
34VCC1V51.5VHP: 1.2V to 1.8VDDR3 memory interface.
35VCC1V51.5VHP: 1.2V to 1.8VDDR3 memory interface.
36VCC1V51.5VHP: 1.2V to 1.8VDDR3 memory interface.

114

115

116

117

118

MGTAVCC_FPGA

MGTVCCAUX_FPGA

MGTAVTT_FPGA

1.0V

1.8V

1.2V

MGT bank supply voltage

MGT bank auxiliary supply voltage

MGT bank termination circuits voltage

MGT banks with Xilinx GTH transceiver units.
191V81.8VHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs.
 371V81.8VHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs.
 381V81.8VHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs.
 39VIO_B_FMCuserHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs.

Table 19: Range of FPGAs bank voltages.

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All dimensions are given in millimeters.

Image Modified

Figure 4: Physical dimensions of the TEC0330-03 board.

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Hardware revision number is printed on the PCB board together with the model number separated by the dash.

Figure 5: TE0330 board hardware revision number.

Document Change History

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