Page History
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| Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
13 | HR | JM1 | 48 | User | HR-Banks support voltages from 1.2V to 3.3V standards |
34 | HR/HP | JM2 | 18 | User | TE0715-xx-15 has no HP-Banks, Banks 34 and 35 are HR-Banks at this module! Banks 34 and 35 of TE0715-xx-30 are HP-Banks and support voltages from 1.2V to 1.8V max with XC7Z030!standards |
| 35 | HR/HP | JM2 | 50 | User1.8V max with XC7Z030! | as above |
34 | HR/HP | JM3 | 16 | User1.8V max with XC7Z030! | as above |
500 | MIO | JM1 | 8 | 3.3V | - |
501 | MIO | JM1 | 6 | 1.8V | - |
112 | GT | JM3 | 4 Lanes | N/A | - |
112 | GT CLK | JM3 | One Differential Input | N/A | NB! AC coupling capacitors on baseboard required. |
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See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
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Power Rails
Voltages on B2B- Connectors | B2B JM1-Pin | B2B JM2-Pin | B2B JM3-Pin | Input/ Output | Note |
|---|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | - | Input | supply voltage |
| 3.3VIN | 13, 15 | - | - | Input | supply voltage |
| VCCIO13 | 9, 11 | - | - | Input | high range bank voltage |
| VCCIO34 | - | 5 | - | Input | TE0715-xx-15: high range bank voltage, TE0715-xx-30: high performance bank voltage |
| VCCIO35 | - | 7, 9 | - | Input | TE0715-xx-15: high range bank voltage, TE0715-xx-30: high performance bank voltage |
| VBAT_IN | 79 | - | - | Input | RTC battery-buffer supply voltage |
| 3.3V | - | 10, 12, 91 | - | Output | intern internal 3,3V Voltage-Level.3V voltage level |
| 1.8V | 39 | - | - | Output | intern internal 1,8V Voltage-Level.8V voltage level |
| 1.5V | - | 19 | - | Output | intern internal 1,5V Voltage-Level.5V voltage level |
| USB_VBUS | - | - | Pin 55 | Input | external 5V USB-Bus Power-Supplypower supply, if needed |
| GND | F1, F2 | F1, F2 | F1, F2 | - | - |
Bank Voltages
Bank |
|---|
| Schematic Name | Voltage | TE0715-xx- |
|---|
15 | TE0715-xx- |
|---|
30 | ||||
|---|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | - | - |
| 501 | VCCO_MIO1_501 | 1.8V | - | - |
| 502 | VCCO_DDR_502 | 1.5V | - | - |
| 0 Config | VCCO_0 | 3.3V | - | - |
| 13 HR | VCCO_13 | User | HR: 1.2V to 3.3V |
| HR: 1.2V to 3.3V |
| 34 HR/HP | VCCO_34 | User |
| HR: 1.2V to 3.3V |
| HP: 1.2V to 1.8V |
| 35 HR/HP | VCCO_35 | User | HR: 1.2V to 3.3V |
| HP: 1.2V to 1.8V |
Technical Specifications
Recommended Operating Conditions
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Document Change History
Date | RrevisionRevision | Contributors | Description |
|---|---|---|---|
| 2016-10-18 | A.N.: added table "power rails" | ||
| 2016-06-28 | V38
| Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pinout Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. |
| 2016-04-27 | V33 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis | Added the table "Recommended Operating Conditions" Storage Temperature edited. |
| 2016-03-31 | V10 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz | Initial version. |
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