Product Specification

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Port Description

Name	Direction	Pin	Description
JTAGEN	in	82	Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA)
M_TMS	in	90
M_TCK	in	91
M_TDI	in	94
M_TDO	out	95
C_TMS	out	85
C_TCK	out	81
C_TDI	out	84
C_TDO	in	83
S1	in	75
S2	in	74
CM0	in	67
CM1	in	66
NOSEQ	inout	29
EN1	out	53
RESIN	out	54
MODE	out	28
PGOOD	inout	27
SDA	inout		???
SCL	inout		???
MIO10	inout
MIO11	inout
MIO12	inout
MIO13	inout
MIO14	inout		UART0.RX << BDBUS0
MIO15	inout		UART0.TX >> BDBUS1
ADBUS4	out
ADBUS7	in
ACBUS4	in
ACBUS5	in
BDBUS0	inout
BDBUS1	inout
USB_OC	in
SD_DETECT	in
SD_WP	in
VID0	out
VID1	out
VID2	out
EN_FMC	out
PG_C2M	out
POK_FMC	in	36
PHY_LED1	out	45
PHY_LED2	out	47
PHY_LED1_A	out	49
PHY_LED2_A	out	48
LED1	out	78
LED2	out	77
LED3	out	76
LED4	out	65
LED5	out	71
LED6	out	70
LED7	out	69
LED8	out	68
dummy	out	51

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