Page History
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Table of contents
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Overview
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Feature Summary
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Firmware Revision and supported PCB Revision
Product Specification
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Port Description
Name | Direction | Pin | Description |
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JTAGEN | in | 82 | Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA) |
M_TMS | in | 90 | |
M_TCK | in | 91 | |
M_TDI | in | 94 | |
M_TDO | out | 95 | |
C_TMS | out | 85 | |
C_TCK | out | 81 | |
C_TDI | out | 84 | |
C_TDO | in | 83 | |
S1 | in | 75 | |
S2 | in | 74 | |
CM0 | in | 67 | |
CM1 | in | 66 | |
NOSEQ | inout | 29 | |
EN1 | out | 53 | |
RESIN | out | 54 | |
MODE | out | 28 | |
PGOOD | inout | 27 | |
SDA | inout | ??? -Delete | |
SCL | inout | ???-Delete | |
MIO10 | inout | 32 | -not used |
MIO11 | inout | 31 | -not used |
MIO12 | inout | 39 | -not used |
MIO13 | inout | 34 | -not used |
MIO14 | inout | 40 | UART0.RX << BDBUS0 |
MIO15 | inout | 30 | UART0.TX >> BDBUS1 |
ADBUS4 | out | 98 | |
ADBUS7 | in | 97 | |
ACBUS4 | in | 96 | |
ACBUS5 | in | 88 | |
BDBUS0 | inout | 87 | |
BDBUS1 | inout | 86 | |
USB_OC | in | 99 | |
SD_DETECT | in | 42 | |
SD_WP | in | 43 | |
VID0 | out | 37 | |
VID1 | out | 38 | -currently work on 35(EN_FMC) |
VID2 | out | 41 | |
EN_FMC | out | 35 | -currently work on 31 (MIO11) |
PG_C2M | out | ??? -Delete | |
POK_FMC | in | 36 | currently not used |
PHY_LED1 | out | 45 | |
PHY_LED2 | out | 47 | |
PHY_LED1_A | out | 49 | |
PHY_LED2_A | out | 48 | |
LED1 | out | 78 | |
LED2 | out | 77 | |
LED3 | out | 76 | |
LED4 | out | 65 | |
LED5 | out | 71 | |
LED6 | out | 70 | |
LED7 | out | 69 | |
LED8 | out | 68 | |
dummy | out | 51 | --remove unused pin |
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Functional Description
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Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Overview
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