Page History
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Name | Direction | Pin | Description |
---|---|---|---|
ACBUS4 | in | 96 | FTDI / currently_not_used |
ACBUS5 | in | 88 | FTDI / currently_not_used |
ADBUS4 | out | 98 | FTDI / get M_TCK |
ADBUS7 | out | 97 | FTDI / currently_not_used |
BDBUS0 | inout | 87 | FTDI / Module UART0.RX << FTDI |
BDBUS1 | inout | 86 | FTDI /Module UART0.TX >> FTDI |
C_TCK | out | 81 | JTAG FTDI |
C_TDI | out | 84 | JTAG FTDI |
C_TDO | in | 83 | JTAG FTDI |
C_TMS | out | 85 | JTAG FTDI |
CM0 | in | 67 | DIP Switch S3-M1 |
CM1 | in | 66 | DIP Switch S3-M2 |
EN_FMC | out | 35 | VADJ Power on |
EN1 | out | 53 | Power Enable Pin for Module CPLD |
JTAGEN | -- | 82 | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) DIP Switch S3-JTAGEN |
JTAGMODE | out | 58 | Enable JTAG access to CPLD for Firmware update on module CPLD (zero: JTAG routed to module FPGA, one: Module CPLD access) |
M_TCK | in | 91 | JTAG Module |
M_TDI | in | 94 | JTAG Module |
M_TDO | out | 95 | JTAG Module |
M_TMS | in | 90 | JTAG Module |
MIO10 | inout | 32 | MIO / used by RGPIO Bus |
MIO11 | inout | 31 | MIO / used by RGPIO Bus |
MIO12 | inout | 39 | MIO / used by RGPIO Bus |
MIO13 | inout | 34 | MIO / used by RGPIO Bus |
MIO14 | inout | 40 | MIO / Module UART0.RX << BDBUS0 |
MIO15 | inout | 30 | MIO / Module UART0.TX >> BDBUS1 |
MODE | out | 28 | Boot Mode for Zynq Devices (Flash or SD) |
NOSEQ | inout | 29 | / currently_not_used |
PGOOD | inout | 27 | / currently_not_used |
PHY_LED1 | out | 45 | LED Ethernet |
PHY_LED1_A | out | 49 | LED Ethernet / currently_not_used |
PHY_LED2 | out | 47 | LED Ethernet |
PHY_LED2_A | out | 48 | LED Ethernet / currently_not_used |
POK_FMC | 36 | LED Ethernet / currently_not_used | |
RESIN | out | 54 | Module Reset |
S1 | in | 75 | User Button / used by RGPIO Bus |
S2 | in | 74 | User Button / Global Reset |
SD_DETECT | in | 42 | SD Detection / used for FPGA Boot Mode |
SD_WP | in | 43 | SD / RGPIO Bus |
ULED1 | out | 78 | LED D6 |
ULED2 | out | 77 | LED D7 |
ULED3 | out | 76 | LED D8 |
ULED4 | out | 65 | LED D9 |
ULED5 | out | 71 | LED D4 |
ULED6 | out | 70 | LED D15 |
ULED7 | out | 69 | LED D14 |
ULED8 | out | 68 | LED D5 |
USB_OC | in | 99 | |
USR0 | in | 64 | DIP Switch S4-1 / used by RGPIO Bus (PCB REV04 only) |
USR1 | in | 61 | DIP Switch S4-2 / used by RGPIO Bus (PCB REV04 only) |
USR2 | in | 60 | DIP Switch S4-3 / used by RGPIO Bus (PCB REV04 only) |
USR3 | in | 59 | DIP Switch S4-4 / used by RGPIO Bus (PCB REV04 only) |
VID0 | out | 37 | VADJ Voltage selection (EN5335QI) |
VID1 | out | 38 | VADJ Voltage selection (EN5335QI) |
VID2 | out | 41 | VADJ Voltage selection (EN5335QI) |
X6 | in | 19 | RGPIO Bus |
Y0 | 15 | / currently_not_used | |
Y1 | 14 | / currently_not_used | |
Y2 | in | 13 | RGPIO CLK |
Y3 | out | 10 | RGPIO TX |
Y4 | in | 9 | RGPIO RX |
Y5 | 8 | / currently_not_used | |
Y6 | in | 7 | RGPIO Bus |
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Functional Description
JTAG
JTAGENB JTAGEN set carrier board CPLD into the Chain chain for Firmware firmware update. In normal mode every FMC JTAG will be set into the chain, when his FMCx_PRSNT is detected.
Power
Reset
Bootmode
RGPIO
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JTAG is routed directly to Module. Set S3-ENJTAG to off to get access to carrier CPLD.
JTAGMODE set module CPLD into the chain for firmware update. In normal mode JTAG is routed directly to FPGA. Set S3-ENJTAG, S3-M1 and S3-M2 to on to get access to module CPLD. Attention VADJ is set to 1.8V in this mode.
Power
EN1 is set to logical one after delay.
EN_FMC is set to logical one after delay.
Reset
RESIN (negative Reset) can be set by S2 Button.
Bootmode
Boot Mode is set to SD-Boot, when SD-Card is detected
RGPIO
RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.
RGPIO Pin to FPGA | Value |
---|---|
24-27 | reserved |
28-31 | Interface detection |
RGPIO Pin from FPGA | Value |
---|---|
0-7 | LED 1-7 |
08-23 | unused |
24-27 | reserved |
28-31 | Interface detection |
LED
UART
Appx. A: Change History and Legal Notices
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