Page History
...
| S5-1 | S5-2 | Description |
|---|---|---|
| ON | ON | Default, boot from SD/microSD or SPI Flash if no SD is detected |
| OFF | ON | Boot mode PJTAG0from eMMC |
| ON | OFF | Boot from eMMCmode PJTAG0 |
| OFF | OFF | Boot mode main JTAG |
...
| LED3 D7 Red (near FAN1 connector on PCB) | ||
|---|---|---|
| Bode Mode | Blink Sequence | Comment |
| Error | ******** | ATX Power failed or PCB is powered offERROR |
| JTAG | *****ooo | Module Low Power Domain failedJTAG |
| PJTAG0 | ****ooooModule | Full Power Domain failedBoot Mode is set to PJTAG0 |
| eMMC | ***oooooModule PL Power Domain failed | Boot Mode is set to eMMC |
| SPI Boot | **ooooooCarrier 1V8 or FMC VADJ Power Domain failed | Boot Mode is set to QSPI |
| SD Boot | *oooooooModule DDR, PL GT, PS GT or PLL Power Domain failed | Boot Mode is set to SD |
| ON | Reset is on | |
| XMOD LED Red (XMOD1 on J12 with green dot) | ||
|---|---|---|
| Status | Blink Sequence | Comment |
| PS_INIT_B | ******** | Indicates the PS is not initialized after a power-on reset (POR). |
| PS_ERROR_OUT | *****ooo | The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU. |
| DONE | ON or OFF | Indicates the PL configuration is completed (LED is OFF). |
| LED_P/N (BLUE Power LED on enclosure) | ||
|---|---|---|
| Status/ User | Blink Sequence | Comment |
| Power | ******** (slow blink) | Indicate board is powered off. |
| RGPIO controlled | User Defined | RGPIO 14 and 15, if RGPIO is active. |
| MIO40 | User Defined | MIO40, if RGPIO is deactivated |
| HDLED_P/N (Red HD LED on enclosure) | ||
|---|---|---|
| Status/ User | Blink Sequence | Comment |
| PS_INIT_B | ******** | Indicates the PS is initialized after a power-on reset (POR). |
| PS_ERROR_OUT | *****ooo | The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU. |
| ERR_STAT | ****oooo | The PS_ERROR_STATUS indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status. |
| RGPIO controlled | User Defined | RGPIO 16 and 17, if RGPIO is active |
| SC0 | User Defined | SC0 (PL IO), if RGPIO is deactivated |
Blink Frequency:
| Blink Sequence | Comment |
|---|---|
| ******** | ~5,8 Hz |
| *****ooo | ~0,7 Hz, duty cycle 5/8 |
| ****oooo | ~0,7 Hz, duty cycle 4/8 |
| ***ooooo | ~0,7 Hz, duty cycle 3/8 |
| **oooooo | ~0,7 Hz, duty cycle 2/8 |
| *ooooooo | ~0,7 Hz, duty cycle 1/8 |
Appx. A: Change History
Revision Changes
CPLD REV04 REV05 to REV05REV06
LED Status changes of LED D2 D3 and HD_LED, XMOD LED
extended Power Management
...
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV06 | REV02, REV03, REV04 |
|
| ||||||||||||||||||||||
| 2017-11-15 | v.38 | REV06 | REV02, REV03, REV04 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-10-18 | v.36 | REV06 | REV02, REV03, REV04 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-06-20 | v.29 | REV05 | REV02, REV03, REV04 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-06-09 | v.28 | REV05 | REV02, REV03, REV04 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-06-08 | v.23 | REV05 | REV02, REV03, REV04 | John Hartfiel | document
| ||||||||||||||||||||||
| 2017-05-08 | v.22 | REV05 | REV02, REV03, REV04 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-02-08 | v.19 | REV04 | REV02, REV03, REV04 | John Hartfiel |
| ||||||||||||||||||||||
| 2016-04-11 | v.1 | --- |
|
| |||||||||||||||||||||||
| All |
|
...
Overview
Content Tools