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JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.
Power
Enable
Reset
Boot Mode
S4-1 | S4-2 | |
---|---|---|
ON | ON | Default, boot from SD/eMMC or SPI Flash if no SD is detected |
OFF | ON | Boot mode PJTAG0 |
ON | OFF | Boot from eMMC |
OFF | OFF | Boot mode main JTAG |
RGPIO
RGPIO Pin to FPGA | Value |
---|
0 | SW1 |
1 | SW2 |
2 | RST_BTN |
3 | PWR_BTN |
4 | SD_CD_S |
5 | SD_CD_B |
6 | F1SENSE |
7 | PWROK |
8 | XMOD_BTN |
9-19 | unused |
20 | PLL_LOL |
21-23 | unused |
24-27 | reserved |
28-31 | Interface detection |
RGPIO Pin from FPGA | Value |
---|---|
0 | PLL_RSTn |
1 | SRSTn |
2 | MRESETn |
3 | PERSTn |
4 | PROG_B |
5 | LED2 |
6 | LED3 |
7 | LED_N |
8 | LED_P |
9 | HDLED_N |
10 | HDLED_P |
11 | FMC_FAN_EN |
12-23 | unused |
24-27 | reserved |
28-31 | Interface detection |
LED
Appx. A: Change History and Legal Notices
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