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JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.
Power
PSON signal will be enabled/disabled after delay, when Power Button is pressed.
ATX PSON is set by PSON signal. This enable/disable 12V power supply from ATX connector.
PCI and SFP Power is always enabled, if 12V is available.
Module 3.3V is always enabled, if 12V is available.
Baseboard 3.3V is always enabled, if 12V is available.
Module PS LPL Power is always enabled, if 12V is available.
Module PS FPD Power is always enabled, if 12V is available.
Module PL Power is always enabled, if 12V is available.
Module DDR Power is always enabled, if 12V is available.
Module PLL Power is always enabled, if 12V is available.
Module PS GT Power is always enabled, if 12V is available.
Module PL GT L/R Power is always enabled, if 12V is available.
| Note |
|---|
TE0808 module is not completely powered off with power button, if 12V power jack (J25) is used for power supply. 12V Power ON/OFF is currently only for ATX connector implemented. |
Enable
SD's will be enabled by PSON.
FMC_FAN_EN will be enabled by PSON or RGPIO (11) controlled, when active.
Reset
| Name | Description |
|---|---|
| PLL_RSTn | not RGPIO (0) when active else '1' |
| SRSTn | not RGPIO (1) when active else '1' |
| MRESETn | not RGPIO (2) when active else RST_BTN |
| PERSTn | not RGPIO (3) when active else PWR_BTN |
| Master CPLD Reset | with PSON and Reset Button over CPLD interconnect. |
Boot Mode
| S4-1 | S4-2 | Description |
|---|---|---|
| ON | ON | Default, boot from SD/eMMC or SPI Flash if no SD is detected |
| OFF | ON | Boot mode PJTAG0 |
| ON | OFF | Boot from eMMC |
| OFF | OFF | Boot mode main JTAG |
UART
XMOD_TXD is sourced by MIO43 and MIO42 by XMOD_RXD.
Module SI5345
Module U5 Selection Pins are set fix to zero.
RGPIO
| RGPIO Pin to FPGA | Value |
|---|---|
| 0 | SW1 |
| 1 | SW2 |
| 2 | RST_BTN |
| 3 | PWR_BTN |
| 4 | SD_CD_S |
| 5 | SD_CD_B |
| 6 | F1SENSE |
| 7 | PWROK |
| 8 | XMOD_BTN |
| 9-19 | unused |
| 20 | PLL_LOL |
| 21-23 | unused |
| 24-27 | reserved |
| 28-31 | Interface detection |
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| Name | Description |
|---|---|
| LED2 D6 Green | RGPIO (5) when active else slow_blink when PS PSON is off else on |
| LED3 D7 Red | RGPIO (6) when active else not RST_BTN or mode_blink |
| LED_N | RGPIO (7) when active else off |
| LED_P | not RGPIO (8) when active else slow_blink when PS PSON is off else on |
| HDLED_N | RGPIO (9) when active else off |
| HDLED_P | not RGPIO (10) when active else reset Button is pressed |
| XMOD_LED Red | Done Pin: ON is not programmed, OFF programmed |
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV04 | REV02, REV03, REV04 |
| Work in progressRevision 04 finished | ||||||||||||||||||||||
| 2016-04-11 | v.1 | --- |
| Initial release | |||||||||||||||||||||||
| All |
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