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Table of Contents

Table of Contents

Overview


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Refer to https://wiki.trenz-electronic.de/display/PD/

...

TE0720+TRM for online version of this manual and additional technical documentation of the product.



 The Trenz Electronic TE0720 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020 or XC7Z014S) with up to 1 GB of DDR3/L SDRAM, 32MB of SPI flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. See also Variants Currently in Production section.

Key Features

  • Xilinx XC7Z SoC (XC7Z020 or XC7Z014S)
      - Processing System: Dual
      • Processing system (PS):
        • XC7Z020: Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
        • XC7Z014S: Single-core ARM Cortex-A9

           Unified 512 KByte L2 cache
           256 KByte on-chip memory
           54 multiplexed I/O pins (MIOs)
      - Programmable Logic
        • MPCore™ with CoreSight™
        • L1 cache: 32 KByte instruction, 32 KByte data per processor
        • L2 cache: Unified 512 KByte
      • Programmable logic (PL): Artix-7 FPGA
               85 K
            • Programmable logic cells

               560 KByte extensible block RAM (140x 36 Kbit BRAM blocks)
               220 programmable DSP slices
               Dual 12-bit 1Msps AD converter
               200
            • : 85K (XC7Z020), 65K (XC7Z014S)
            • Block RAM: 4.9 MByte (XC7Z020), 3.8 MByte (XC7Z014S)
            • DSP slices:  220 (XC7Z020), 170 (XC7Z014S)
            • Peak DSP performance: 276 GMACs (XC7Z020), 187 GMACs (XC7Z014S)
            • 2x 12 bit, MSPS ADCs with up to 17 differential inputs
        • 54 multiuse I/O (MIO) pins
        • 152 High-Range (HR) I/O pins (SelectIO interfaces)
        • System Controller CPLD (Lattice LCMXO2-1200HC)
        • Up to 1 GByte DDR3/L SDRAM memory , (2 x 256 Mbit x 16 (, 32-bit wide data bus).
        • 32 MByte Quad SPI Flash memory
        • Gigabit Ethernet transceiver PHY (Marvell 88E1512)
        • MAC address serial EEPROM with EUI-48™ node identity (11AA02E48)
        • Highly integrated Highly Integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK)
        • 3-axis accelerometer and 3-axis magnetometer (ST Microelectronics LSM303DTR) (Not installedOptional!) 
        • Real time clock with embedded crystal (Intersil ISL12020M): ±5ppm accuracy
        • Atmel CryptoAuthentication element (Atmel ATSHA204A)
        • Up to 32 GByte eMMC, usually 4 GByte, depends on module variant and assembly option
        • User LED 1 (Green), user LED 2 (Red), user LED 3 - FPGA DONE (Green)
        • 1.5A, PowerSoC DC-DC step-down converter (Enpirion EP53F8QI) for 1.8V power supply
        • 1.5A, PowerSoC DC-DC step-down converter (Enpirion EP53F8QI) for 1.5V power supply
        • 4A PowerSoC DC-DC step-down converter (Enpirion EN6347) for 1.0V power supply
        • On-board high-efficiency DC-DC converters for all voltages used
        • Trenz Trenz 4 x 5 module socket connector connectors (3 x Samtec LSHM series connectors)
        • Evenly spread supply pins for good signal integrity
        • Rugged for shock and high vibration

        Additional assembly options are available for cost or performance optimization upon request.

        Page break

        Block Diagram

        Figure 1: TE0720-03 block diagram.

        Components and connections marked with dashed lines are optional or may be missing on some module variants, please contact us for additional information.

        Main Components

         

        Figure 2: Main components of the module.

        1. Xilinx Zynq XC7Z SoC, U5
        2. 4 Gbit DDR3/L SDRAM, U13
        3. 4 Gbit DDR3/L SDRAM, U12
        4. Low-power RTC with battery backed SRAM, U20
        5. 32 MByte Quad SPI Flash memory, U7
        6. Red LED (LED1LED2), D5
        7. Green LED (LED2LED1), D2
        8. System Controller CPLD, U19
        9. eMMC NAND Flash, U15
        10. 4A high-efficiency PowerSoC DC-DC step-down Converter converter (1V), U1
        11. Green LED (DONE), D4
        12. B2B connector Samtec Razor Beam™ LSHM-130, JM3
        13. B2B connector Samtec Razor Beam™ LSHM-150, JM1
        14. B2B connector Samtec Razor Beam™ LSHM-150, JM2
        15. Hi-speed USB 2.0 ULPI transceiver, U18
        16. Gigabit Ethernet (GbE) transceiver, U8
        17. Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
        18. Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
        19. Low-dropout regulator (VBATT), U24
        20. DDR termination regulator, U4
        21. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
        22. Atmel CryptoAuthentication chip, U10
        23. 2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
        24. Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
        25. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
        26. 3A PFET load switch with configurable slew rate (3.3V), Q1

        ...

        Storage device name

        		IC

        Content

        Notes

        Quad SPI Flash

        		U7

        Empty

        		-
        eMMC NAND FlashU15Empty-
        11AA02E48T EEPROMU17

        Pre-programmed globally unique, 48-bit node address (MAC)

        		-
        System Controller CPLDU19Standard firmware.Download firmware

        Signals, Interfaces and Pins

        Board to Board (B2B) I/Os

        I/O signals connected to the SoC's IO bank and B2B connector: 

        Table 1: Initial state of programmable devices on delivery of the module.

        Boot Process

        By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

        MODE Signal State

        		Boot Mode

        High or open

        QSPI

        Low or connected to the ground

        SD Card

        Table 14: Boot modes.

        Signals, Interfaces and Pins

        Board to Board (B2B) I/Os

        PL I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 152 HR GPIOs total.

        8 MIOs
        BankTypeVoltageB2BI/O CountBankTypeB2B ConnectorI/O Signal CountVoltageNotes
        13HR GPIOVCCIO13JM248 I/Os, 24 LVDS pairsVCCIO13 
        13HR GPIOVCCIO13JM22 I/OsVCCIO13B13_IO0 and B13_IO25
        33HR GPIOVCCIO33JM218 I/Os, 9 LVDS pairsVCCIO33 
        34HR GPIOVCCIO34JM336 I/Os, 18 LVDS pairsVCCIO34 
        35HR GPIOVCCIO35JM148 I/Os, 24 LVDS pairsVCCIO35 500MIOJM1

        Table 2: General PL I/O to B2B connectors information.


        PS MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.

        MIOB2B PinBankVoltageNotes
        0JM1-875003.3V
         501MIOJM16 MIOs1.8V 

        For detailed information about the pin-out, please refer to the Pin-out tables. 

        JTAG Interface

        JTAG access to the Xilinx Zynq and to the System Controller CPLD is provided through B2B connector JM2.

        ...

        JTAG Signal

        ...

        B2B Connector Pin

        ...

        Note
        JTAGMODE pin 89 in B2B connector JM1 is used to select which device is accessible. Low - Xilinx Zynq, High - System Controller CPLD.

        Page break

        System Controller I/O Pins

        Special purpose pins are connected to System Controller CPLD and have following default configuration:

        ...


        9JM1-915003.3V
        10JM1-955003.3V
        11JM1-935003.3V
        12JM1-995003.3V
        13JM1-975003.3V
        14JM1-925003.3VAlso wired to U19-M4
        15JM1-855003.3VAlso wired to U19-N4
        40JM1-275011.8VZynq SoC SD0
        41JM1-255011.8VZynq SoC SD0
        42JM1-235011.8VZynq SoC SD0
        43JM1-215011.8VZynq SoC SD0
        44JM1-195011.8VZynq SoC SD0
        45JM1-175011.8VZynq SoC SD0

        Table 3: General PS MIO connections information.


        For detailed information about the pin-out, please refer to the Pin-out tables. 

        JTAG Interface

        JTAG access to the Zynq SoC and System Controller CPLD is provided through B2B connector JM2.

        JTAG Signal

        B2B Connector Pin

        TMSJM2-93
        TDIJM2-95
        TDOJM2-97
        TCKJM2-99

        Table 4: JTAG pins connection.


        Note
        JTAGMODE pin 89 in B2B connector JM1 is used to switch access between devices, low selects Zynq SoC, high selects System Controller CPLD.

        System Controller CPLD I/O Pins

        Special purpose pins are connected to System Controller CPLD and have following default configuration:

        Pin NameModeFunctionDefault Configuration
        RESINInputReset inputActive low reset input, default mapping forces POR_B reset to Zynq PS.
        PGOODOutputPower goodActive high when all on-module power supplies are working properly.
        MODEInputBoot modeForce low for boot from the SD card. Latched at power-on only, not during soft reset!
        EN1InputPower enableHigh enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high.
        NOSEQInputPower sequencingForces the 1.0V and 1.8V DC-DC converters always ON when high.
        JTAGMODEInputJTAG selectKeep low for FPGA JTAG access.
        MIO7Input/OutputGPIOConnected to System Controller CPLD pin P11, function depends on firmware

        Table 5: System Controller CPLD special purpose pins description.

        Page break

        Quad SPI Interface

        Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.

        MIOSignal NameU7 Pin
        1SPI-CSC2
        2SPI-DQ0/M0D3
        3SPI-DQ1/M1D2
        4SPI-DQ2/M2C4
        5SPI-DQ3/M3D4
        6SPI-SCK/M4B2

        Table 6: Quad SPI interface MIOs and pins.

        eMMC Interface

        The TE0720 has on-board eMMC memory device (U15) except TE0720-03-1CR variant. At least three different eMMC devices have been used, please contact Trenz Electronic for more specific information.

        MIOSignal NameU15 Pin
        46MMC-D0H3
        47MMC-CMDW5
        48MMC-CLKW6
        49MMC-D1H4
        50MMC-D2H5
        51MMC-D3J2

        Table 7: eMMC interface MIOs and pins.

        Page break

        Ethernet Interface

        The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see tables below.

        SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).

        Ethernet PHY to B2B connections

         PHY SignalB2B Pin
        		PHY SignalB2B Pin
        SOUT_NJM3-1
        		PHY_MDI1_PJM1-10
        SOUT_PJM3-3
        		PHY_MDI1_NJM1-12
        SIN_NJM3-2
        		PHY_MDI2_PJM1-16
        SIN_PJM3-4
        		PHY_MDI2_NJM1-18
        PHY_MDI0_PJM1-4
        		PHY_MDI3_PJM1-22
        PHY_MDI0_NJM1-6
        		PHY_MDI3_NJM1-24

        Table 8: Ethernet PHY to B2B connections.


        Ethernet PHY to Zynq SoC PS MIO ETH0 connections

        PHY SignalSoC MIO
        		PHY SignalSoC MIO
        ETH-TXCK16
        		ETH-RXCK22
        ETH-TXD017
        		ETH-RXD023
        ETH-TXD1

        18


        		ETH-RXD124
        ETH-TXD219
        		ETH-RXD225
        ETH-TXD320
        		ETH-RXD326
        ETH-TXCTL21
        		ETH-RXCTL27
        ETH-MDC52
        		ETH-MDIO53

        Table 9: Ethernet PHY to Zynq SoC connections.

        Page break

        USB Interface

        Hi-speed USB ULPI PHY is provided by USB3320 from Microchip (U18). The ULPI interface is connected to the Zynq SoC PS USB0 via MIO28..39, bank 501.

        USB PHY SignalWired toSoC MIO
        OTG-DATA4U18-728
        OTG-DIRU18-31

        29

        OTG-STPU18-2930
        OTG-NXTU18-231
        OTG-DATA0U18-332
        OTG-DATA1U18-433
        OTG-DATA2U18-534
        OTG-DATA3U18-635
        OTG-CLKU18-136
        OTG-DATA5U18-937
        OTG-DATA6U18-1038
        OTG-DATA7U18-1339

        Table 10: USB ULPI PHY to Zynq SoC connections.


        USB PHY connection

        USB PHY PinSC CPLD PinB2B NameNotes
        REFSEL0..2--Reference clock frequency select, all set to GND = 52.000000 MHz.
        RESETBB14, bank 1-Active low reset.
        CLKOUT--ULPI output clock connected to Zynq PS MIO36.
        DP, DM
        		OTG-D_P, OTG-D_NUSB data lines.
        CPEN
        		VBUS_V_ENExternal USB power switch active high enable signal.
        VBUS-USB-VBUSConnect to USB VBUS via a series of resistors, see reference schematic.
        ID-OTG-IDFor A-device connect to the ground, for B-device leave floating.
        SPK_LM5, bank 2-In USB audio mode a switch connects the DM pin to the SPK_L.
        SPK_RM8, bank 2-In USB audio mode a switch connects the DP pin to the SPK_R.

        Table 11: USB ULPI PHY connections.

        I2C Interface

        On-board I2C devices are connected to the System Controller CPLD which acts as a I2C bus repeater for the Zynq SoC. System Controller CPLD signals X1, X3 and X7 are routed to Zynq SoC bank 34. Exact functionality depends on the System Controller CPLD firmware.

        Signal NameSC CPLD PinSoC PinNotes
        X1F1L16SCL, I2C clock.
        X5J1P22SDA, I2C data out.
        X7M1N22SDA, I2C data in.

        Table 12: Zynq SoC to System Controller CPLD I2C bus.


        I2C DeviceI2C AddressICNotes
        ISL12020M RTC0x6FU20RTC registers.
        ISL12020M SRAM0x57U20Battery backed RAM in RTC IC.
        LSM303D0x1DU22Optional, not soldered on current production variants.

        Table 13: I2C slave device addresses.

        On-board Peripherals

        System Controller CPLD

        The System Controller CPLD (U19) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). The System Controller CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in System Controller CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Also interfaces like JTAG and I2C between the on-board peripherals and to the Zynq SoC are by-passed, forwarded and controlled.

        Other tasks of the System Controller CPLD are monitoring of the power-on sequence and to indicate the programming state of the Zynq SoC FPGA.

        For more detailed information, refer to the TE0720 System Controller CPLD firmware page.

        DDR Memory

        By default TE0720 module has two DDR3/L SDRAM chips arranged into 32-bit wide memory bus providing total on-board memory size up to 1 GBytes. Size of memory depends on the module variant, refer to the variants table.

        Quad SPI Flash Memory

        On-board 32-MByte QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

        Note

        SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

        eMMC Flash Memory

        eMMC Flash memory device(U15) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51 (see also Variants Currently in Production for options). Depending on the module variant, different make and model of eMMC chips are available.

        Gigabit Ethernet PHY

        On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).


        PHY SignalSC CPLD Pin
        ETH-MDCL14
        ETH-MDIOK14
        PHY_LED0F14
        PHY_LED1D12
        PHY_LED2C13
        PHY_CONFIGC14
        ETH-RSTE14
        CLK_125MHZG13

        Table 15: Ethernet PHY to SC CPLD connections.

        Page break

        High-speed USB ULPI PHY

        Hi-speed USB ULPI PHY is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

        RTC - Real Time Clock

        Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

        MAC-Address EEPROM

        A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD pin M14 via single-I/O UNI/O serial interface and contains pre-programmed globally unique 48-bit node address compatible with EUI-48TM specification. Chip is programmed at the factory with a globally unique node address stored in the upper 1/4 of the memory array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use.

        Atmel CryptoAuthentication Chip

        The ATSHA204A Atmel CryptoAuthenticationTM chip (U10) is connected to the System Controller CPLD pin N14 via single-wire interface providing various security functions and features such as anti-counterfeiting, firmware/media protection, password validation, secure session key exchanging, secure data storage and more. Refer to the product datasheet for more information.

        eCompass module

        Optionally TE0720 module can be fitted with ultra-compact high-performance eCompass device (LSM303D, U22) featuring 3D accelerometer and 3D magnetometer.

        Oscillators

        SourceSignalFrequencyDestinationPin NameNotes
        U6

        PS-CLK

        33.333333 MHz

        U5

        PS_CLK_500

        Zynq SoC PS subsystem main clock.

        U14

        OTG-RCLK

        52.000000 MHz

        		U18

        REFCLK

        USB3320C PHY reference clock.

        U9ETH-CLK25.000000 MHzU8XTAL_IN88E1512 PHY reference clock.

        Table 16: Oscillators.

        On-board LEDs

        LEDColorConnected toDescription and Notes
        D2GreenLED1Controlled by System Controller CPLD firmware.
        D4GreenDONE
        D5RedLED2Controlled by System Controller CPLD firmware.

        Table 17: On-board LEDs

        On-board LEDs

        ...

        Clocking

        ...

        PS-CLK

        ...

        33.333333 MHz

        ...

        U6

        ...

        PS_CLK_500

        ...

        PS subsystem main clock.

        ...

        OTG-RCLK

        ...

        52.000000 MHz

        ...

        -

        ...

        USB3320C reference clock.

        ...

        Page break

        Default MIO Mapping

        ...

        Page break

        Gigabit Ethernet

        On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).

        Ethernet PHY connection

        ...

        Page break

        USB Interface

        USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and reference clock input of the PHY is supplied from the on-board 52.000000 MHz oscillator (U14).

        USB PHY connection

        ...

        The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.

        I2C Interface

        On-board I2C devices are connected to the System Controller CPLD, device slave addresses are listed in the table below:

        ...

        Boot Process

        By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

        ...

        MODE Signal State

        ...

        High or open

        ...

        SD Card

        ...

        Low or connected to the ground

        ...

        QSPI

        On-board Peripherals

        32 MByte Quad SPI Flash Memory

        On-board QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

        Note

        SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

        Processing System (PS) Peripherals

        ...

        MIO16..27

        MIO52..53

        ...

        1) Different make and model may be installed on different module variants.

        RTC - Real Time Clock

        Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

        MAC-Address EEPROM

        A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.

        Power and Power-On Sequence

        ...

        Power Input PinTypical Current
        VINTBD*
        3.3VINTBD*

        Table 18: Power Consumption.

         * TBD - To Be Determined soon with reference design setup.

        Power Distribution Diagram

        Image Removed

        .


        Power Distribution Diagram

        Image Added

        Figure 3: Power distribution diagram.

        Note

        Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).


        Page break

        Power-On Sequence

        For highest efficiency of the on-board DC-DC regulators, it is recommended to use same single 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

        It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

        Use 3.3V or 1.8V output to enable external power supplies or power switches which are used to supply FPGA banks.

        See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.

        ...

        NOSEQ input signal from the carrier board can be used to control output of the two DC-DC converters U1 and U3. It works in conjunction with the System Controller CPLD firmware controlled ON_1V0 and ON_1V8 input signals of the U21 and U25 gate ICs.

         


        If NOSEQ input signal from the carrier board is low (logical 0), signals ON_1V0 and ON_1V8 can be driven by System Controller CPLD to control outputs of the U1 and U3 DC-DC converters.If NOSEQ input signal from the carrier board is high (logical 1), state of the ON_1V0 and ON_1V8 signals is irrelevant and DC-DC converters U1 and U3 outputs are always enabled.

        Figure 4: Power sequencing.


        Note

        Initial state of the ON_1V0 and ON_1V8 signals and therefore also functionality of the NOSEQ signal depend on the System Controller CPLD firmware.

        Page break

        Power Rails

        B2B Name

        B2B JM1 Pins

        B2B JM2 Pins

        Direction

        		Note
        VIN1, 3, 52, 4, 6, 8InputSupply voltage from carrier board.
        3.3VIN13, 1591-InputSupply voltage from carrier board. JM2-91 is VREF_JTAG..
        JTAG VREF-91Output

        JTAG reference voltage.

        Attention: Net name on schematic is "3.3VIN"

        VCCIO359, 11-InputHigh range bank voltage from carrier board.
        VCCIO33-5InputHigh range bank voltage from carrier board.
        VCCIO13-7, 9InputHigh range bank voltage from carrier board.
        VCCIO34-1, 3InputHigh range bank voltage from carrier board.
        VBAT_IN79-InputRTC battery-buffer supply voltage.
        3.3V-10, 12OutputInternal 3.3V voltage level.
        1.8V39-OutputInternal 1.8V voltage level.
        1.5V 1)-19OutputInternal 1.5V voltage level.

        Table 19: Module power rails.

        1) In case of module variant of TE0720-03-L1IF which uses Xilinx Zynq XC7Z020-L1CLG484I chip with lower power consumption, power rails named 1.5V and VCCO_DDR_502 voltage is actually 1.35V. To achieve this, a resistor with different value is used for R4 (see schematics schematic of the TE0720-03-L1IF for more information).

        Bank Voltages

        Bank          

        		Schematics Schematic Name

        Voltage

        		Notes
        5003.3V, VCCO_MIO0_5003.3V 
        5011.8V, VCCO_MIO1_5011.8V 
        5021.5V, VCCO_DDR_5021.5V 
        0 Config3.3V3.3V 
        1.8V
        5021.5V, VCCO_DDR_5021.5V
        0 Config3.3V3.3V
        13 HRVCCO131.2V to 3.3VSupplied by the carrier board.
        33 HRVCCIO331.2V to 3.3VSupplied by the carrier board.
        34 HRVCCIO341.25V to 3.3V

        Supplied by the carrier board.
        This FPGA Bank Power must be supplied and is not optional.
        Minimum Voltage: B34 signals are used for CPLD/FPGA communication and  for PG generated by (TPS3805H33DCKR)

        35 HRVCCIO3513 HRVCCO131.2V to 3.3V

        Supplied by the carrier board.

        33 HRVCCIO331.2V to 3.3VSupplied by the carrier board.
        34 HRVCCIO341.2V to 3.3VSupplied by the carrier board.
        35 HRVCCIO351.2V to 3.3V

        Supplied by the carrier board.

        Board to Board Connectors

        ...

        Variants Currently in Production

        ...

        RAM

        ...

        eMMC

        Size

        ...

        Temperature

        Range

        ...

        B2B Connector

        Height

        ...

        Table 20: Zynq SoC bank voltages.

        Board to Board Connectors

        Include Page
        4 x 5 SoM LSHM B2B Connectors
        4 x 5 SoM LSHM B2B Connectors

        Variants Currently in Production

        Page properties
        hiddentrue
        idComments
        Note: Only table was changed, chapter must be updated in case of TRM Style update


        Trenz shop TE0720 overview page
        English pageGerman page

        Table 21: Module variants currently in production.

        Technical Specifications

        Absolute Maximum Ratings

        Parameter

        		MinMax

        Units

        Reference Document

        VIN supply voltage

        		-0.36.5

        V

        		EP53F8QI datasheet.
        3.3VIN supply voltage-0.13.75VTPS27082L and LCMXO2-1200HC datasheets.
        Supply voltage for PS MIO banks-0.53.6VSee Xilinx DS187 datasheet.
        I/O input voltage for MIO banks-0.4VCCO_MIO + 0.55V

        See Xilinx DS187 datasheet.

        (VCCO_MIO0_500, VCCO_MIO1_501)

        Supply voltage for HR I/Os banks-0.53.6V

        See Xilinx DS187 datasheet.

        (VCCIO13, VCCIO33, VCCIO34, VCCIO35)

        I/O input voltage for HR I/O banks-0.4VCCIO + 0.55VSee Xilinx DS187 datasheet.

        Storage temperature

        -40

        +85

        °C

        		-
        Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed-55+100°CNB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C.

        Table 22: Module absolute maximum ratings.


        Note
        Assembly variants for higher storage temperature range are available on request.


        Note
        Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings.

        Recommended Operating Conditions

        Technical Specifications

        Absolute Maximum Ratings

        ParameterMinMaxUnitsReference Document
        VIN supply voltage
        -0
        2.
        3
        5
        6
        5.5VEN6347QI and EP53F8QI
        datasheet
        datasheets.
        3.3VIN supply voltage
        -0
        3.
        1
        1353.
        75
        465V
        TPS27082L and LCMXO2-1200HC datasheets
        3.3V +/- 5%.
        Supply voltage for PS MIO banks
        -0
        1.
        5
        713.
        6
        465VSee Xilinx DS187 datasheet.
        I/O input voltage for PS MIO banks-0.
        4
        20VCCO_MIO + 0.
        55
        20VSee Xilinx DS187
        datasheet.(VCCO_MIO0_500, VCCO_MIO1_501)
        datasheet.
        Supply voltage for HR I/Os banks
        -0
        1.
        5
        143.
        6
        465VSee Xilinx DS187 datasheet.

        (VCCIO13, VCCIO33, VCCIO34, VCCIO35)

        I/O input voltage for HR I/O banks-0.
        4
        20VCCIO + 0.
        55
        20VSee Xilinx DS187 datasheet.

        Storage temperature

        -40

        +85

        °C

        -Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed-55+100°CNB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C.
        Note
        Assembly variants for higher storage temperature range are available on request.
        Note
        Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings.

        Recommended Operating Conditions

        ...

        Table 23: Recommended operating conditions.

        Operating Temperature Ranges

        Commercial grade: 0°C to +70°C.

        Industrial and automotive grade: -40°C to +85°C.

        Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

        Physical Dimensions

        • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

        • Mating height with standard connectors: 8 mm.

        • PCB thickness: 1.6 mm.

        • Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

         All dimensions are given in millimeters.

        Image Added     Image Added

        Figure 5: TE0720 module physical dimensions.

        Revision History

        Hardware Revision History

        DateRevision

        Notes

        		PCNDocumentation Link
        2015-10-1203

        		TE0720-03
        -02

        		TE0720-02
        -

        01

        Prototypes



        Table 24: Hardware revision history table.

        There is no hardware revision number marking on the module PCB.

        Document Change History

        Date

        Revision

        Contributors

        Description

        Page info
        infoTypeModified date
        dateFormatyyyy-MM-dd
        typeFlat

        Page info
        infoTypeCurrent version
        prefixv.
        typeFlat

        Page info
        infoTypeModified by
        typeFlat

        • changed currently available chapter to new style
        2021-06-21v.93Mohsen Chamanbaz
        • fix typo for LED location on main component section
        2019-02-05v.92John Hartfiel
        • small document update

        2018-07-05

        		v.89John Hartfiel
        • Update power rail section
        2017-11-10

        v.85

        		John Hartfiel
        • Replace B2B connector section
        2017-09-07

        v.84

        		John Hartfiel
        • Correction of Boot Mode section
        2017-08-31

        v.83

        		Jan Kumann
        • Initial document.

        --

        all

        Page info
        infoTypeModified users
        typeFlat

        • --

        Table 25: Document change history table

        Operating Temperature Ranges

        Commercial grade: 0°C to +70°C.

        Industrial and automotive grade: -40°C to +85°C.

        Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

        Physical Dimensions

        • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

        • Mating height with standard connectors: 8 mm.

        • PCB thickness: 1.6 mm.

        • Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

         All dimensions are given in millimeters.

        Image Removed     Image Removed

        Weight

        ca 23 g - Plain module

        Revision History

        Hardware Revision History

        ...

        Notes

        ...

        01

        ...

        Prototypes

        ...

        Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

        Put pic of PCB silk screen here showing model and revision ...

        Document Change History

        ...

        Date

        ...

        Revision

        ...

        Contributors

        ...

        Description

        ...

        Jan Kumann

        ...

        .

        Disclaimer

        Include Page
        IN:Legal Notices
        IN:Legal Notices