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Table of Contents

Table of Contents

Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TE0720+TRM for online version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0720 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020 or XC7Z014S) with up to 1 GB of DDR3/L SDRAM, 32MB of SPI flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. See also Variants Currently in Production section.

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Xilinx XC7Z SoC (XC7Z020 or XC7Z014S)
- Processing system (PS):
  - XC7Z020: Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
  - XC7Z014S: Single-core ARM Cortex-A9 MPCore™ with CoreSight™
  - L1 cache: 32 KByte instruction, 32 KByte data per processor
  - L2 cache: Unified 512 KByte
- Programmable logic (PL): Artix-7 FPGA
  - Programmable logic cells: 85K (XC7Z020), 65K (XC7Z014S)
  - Block RAM: 4.9 MByte (XC7Z020), 3.8 MByte (XC7Z014S)
  - DSP slices: 220 (XC7Z020), 170 (XC7Z014S)
  - Peak DSP performance: 276 GMACs (XC7Z020), 187 GMACs (XC7Z014S)
  - 2x 12 bit, MSPS ADCs with up to 17 Differential Inputsdifferential inputs
54 multiuse I/O (MIO) pins
152 High-Range (HR) I/O pins (SelectIO interfaces)
System Controller CPLD (Lattice LCMXO2-1200HC)
Up to 1 GByte DDR3/L SDRAM memory , (2 x 256 Mbit x 16 (, 32-bit wide data bus).
32 MByte Quad SPI Flash memory
Gigabit Ethernet transceiver PHY (Marvell 88E1512)
MAC address serial EEPROM with EUI-48™ node identity (11AA02E48)
Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK)
3-axis accelerometer and 3-axis magnetometer (ST Microelectronics LSM303DTR) (Optional!)
Real time clock with embedded crystal (Intersil ISL12020M): ±5ppm accuracy
Atmel CryptoAuthentication element (Atmel ATSHA204A)
Up to 32 GByte eMMC, usually 4 GByte, depends on module variant and assembly option
User LED 1 (Green), user LED 2 (Red), user LED 3 - FPGA DONE (Green)
On-board high-efficiency DC-DC converters for all voltages used
Trenz 4 x 5 module socket connectors (3 x Samtec LSHM series connectors)
Evenly - spread supply pins for good signal integrity
Rugged for shock and high vibration

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Figure 2: Main components of the module, descriptions follow.

Xilinx Zynq XC7Z SoC, U5
4 Gbit DDR3/L SDRAM, U13
4 Gbit DDR3/L SDRAM, U12
Low-power RTC with battery backed SRAM, U20
32 MByte Quad SPI Flash memory, U7
Red LED (LED1LED2), D5
Green LED (LED2LED1), D2
System Controller CPLD, U19
eMMC NAND Flash, U15
4A high-efficiency PowerSoC DC-DC step-down Converter converter (1V), U1
Green LED (DONE), D4
B2B connector Samtec Razor Beam™ LSHM-130, JM3
B2B connector Samtec Razor Beam™ LSHM-150, JM1
B2B connector Samtec Razor Beam™ LSHM-150, JM2
Hi-speed USB 2.0 ULPI transceiver, U18
Gigabit Ethernet (GbE) transceiver, U8
Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
Low-dropout regulator (VBATT), U24
DDR termination regulator, U4
1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
Atmel CryptoAuthentication chip, U10
2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
3A PFET load switch with configurable slew rate (3.3V), Q1

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Table 1: Initial state of programmable devices on delivery of the module.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Boot Process

By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

MODE Signal State	Boot Mode
High or open	QSPI
Low or connected to the ground	SD Card

Table 14: Boot modes.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

PL I/O PL I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 152 HR GPIOs total.

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Table 2: General PL I/O to B2B connectors information.

PS MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.

MIO	B2B Pin	Bank	Voltage	Notes
0	JM1-87	500	3.3V
9	JM1-91	500	3.3V
10	JM1-95	500	3.3V
11	JM1-93	500	3.3V
12	JM1-99	500	3.3V
13	JM1-97	500	3.3V
14	JM1-92	500	3.3V	Also wired to U19-M4
15	JM1-85	500	3.3V	Also wired to U19-N4
40	JM1-27	501	1.8V	Zynq SoC SD0
41	JM1-25	501	1.8V	Zynq SoC SD0
42	JM1-23	501	1.8V	Zynq SoC SD0
43	JM1-21	501	1.8V	Zynq SoC SD0
44	JM1-19	501	1.8V	Zynq SoC SD0
45	JM1-17	501	1.8V	Zynq SoC SD0

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Table 4: JTAG pins connection.

Note
JTAGMODE pin 89 in B2B connector JM1 is used to switch access between devices, low selects Zynq SoC, high selects System Controller CPLD.

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System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

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Ethernet PHY to B2B connections

PHY Signal	B2B Pin	PHY Signal	B2B Pin
SOUT_N	JM3-1	PHY_MDI1_P	JM1-10
SOUT_P	JM3-3	PHY_MDI1_N	JM1-12
SIN_N	JM3-2	PHY_MDI2_P	JM1-16
SIN_P	JM3-4	PHY_MDI2_N	JM1-18
PHY_MDI0_P	JM1-4	PHYPHY_MDI3_P	JM1-22
PHY_MDI0_N	JM1-6	PHY_MDI3_N	JM1-24

Table 8: Ethernet PHY to B2B connections.

Ethernet PHY to Zynq SoC PS MIO ETH0 connections

PHY Signal	SoC MIO	PHY Signal	SoC MIO
ETH-TXCK	16	ETH-RXCK	22
ETH-TXD0	17	ETH-RXD0	23
ETH-TXD1	18	ETH-RXD1	24
ETH-TXD2	19	ETH-RXD2	25
ETH-TXD3	20	ETH-RXD3	26
ETH-TXCTL	21	ETH-RXCTL	27
ETH-MDC	52	ETH-MDIO	53

Table 9: Ethernet PHY to Zynq SoC connections.

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USB PHY Pin	SC CPLD Pin	B2B Name	Notes
REFSEL0..2	-	-	Reference clock frequency select, all set to GND = 52.000000 MHz.
RESETB	B14, bank 1	-	Active low reset.
CLKOUT	-	-	ULPI output clock connected to Zynq PS MIO36.
DP, DM		OTG-D_P, OTG-D_N	USB data lines.
CPEN		VBUS_V_EN	External USB power switch active high enable signal.
VBUS	-	USB-VBUS	Connect to USB VBUS via a series of resistors, see reference schematic.
ID	-	OTG-ID	For A-device connect to the ground, for B-device leave floating.
SPK_L	M5, bank 2	-	In USB audio mode a switch connects the DM pin to the SPK_L.
SPK_R	M8, bank 2	-	In USB audio mode a switch connects the DP pin to the SPK_R.

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Table 13: I²C slave device addresses.

Boot Process

By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

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MODE Signal State

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High or open

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SD Card

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Low or connected to the ground

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QSPI

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U19) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). The System Controller CPLD is the central

Table 14: Boot modes.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U19) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). The System Controller CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in System Controller CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Also interfaces like JTAG and I²C between the on-board peripherals and to the Zynq SoC are by-passed, forwarded and controlled.

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For more detailed information, refer to the TE0720 System Controller CPLD firmware page.

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DDR Memory

By default TE0720 module has two DDR3/L SDRAM chips arranged into 32-bit wide memory bus providing total on-board memory size up to 1 GBytes. Size of memory depends on the module variant, refer to the variants table.

Quad SPI Flash Memory

On-board 32-MByte QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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The ATSHA204A Atmel CryptoAuthentication^TM chip (U10) is connected to the System Controller CPLD pin N14 via single-wire interface providing various security functions and features such as anti-counterfeiting, firmware/media protection, password validation, secure session key exchanging, secure data storage and more. Refer to the product datasheet for more information.

Oscillators

eCompass module

Optionally TE0720 module can be fitted with ultra-compact high-performance eCompass device (LSM303D, U22) featuring 3D accelerometer and 3D magnetometer.

Oscillators

Source	Signal	Frequency	Destination	Pin Name	Source
U6	PS-CLK	33.333333 MHz	U5	PS_CLK_500	Zynq SoC PS subsystem main clock.
U14	OTG-RCLK	52.000000 MHz	U18	REFCLK	USB3320C PHY reference clock.
U9	ETH-CLK	25.000000 MHz	U8	XTAL_IN	88E1512 PHY reference clock.

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LED	Color	Connected to	Description and Notes
D2	Green	LED1	Controlled by System Controller CPLD firmware.
D4	Green	DONE
D5	Red	LED2	Controlled by System Controller CPLD firmware.

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Note
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Page break

Power-On Sequence

For highest efficiency of the on-board DC-DC regulators, it is recommended to use same single 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

Use 3.3V or 1.8V output to enable external power supplies or power switches which are used to supply FPGA banks.

See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.

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NOSEQ input signal from the carrier board can be used to control output of the two DC-DC converters U1 and U3. It works in conjunction with the System Controller CPLD firmware controlled ON_1V0 and ON_1V8 input signals of the U21 and U25 gate ICs.


If NOSEQ input signal from the carrier board is low (logical 0), signals ON_1V0 and ON_1V8 can be driven by System Controller CPLD to control outputs of the U1 and U3 DC-DC converters.	If NOSEQ input signal from the carrier board is high (logical 1), state of the ON_1V0 and ON_1V8 signals is irrelevant and DC-DC converters U1 and U3 outputs are always enabled.

Figure 4: Power sequencing.

Note
Initial state of the ON_1V0 and ON_1V8 signals and therefore also functionality of the NOSEQ signal depend on the System Controller CPLD firmware.

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B2B Name	B2B JM1 Pins	B2B JM2 Pins	Direction	Note
VIN	1, 3, 5	2, 4, 6, 8	Input	Supply voltage from carrier board.
3.3VIN	13, 15	91-	Input	Supply voltage from carrier board. JM2
JTAG VREF	-91 is VREF_JTAG.	91	Output	JTAG reference voltage. Attention: Net name on schematic is "3.3VIN"
VCCIO35	9, 11	-	Input	High range bank voltage from carrier board.
VCCIO33	-	5	Input	High range bank voltage from carrier board.
VCCIO13	-	7, 9	Input	High range bank voltage from carrier board.
VCCIO34	-	1, 3	Input	High range bank voltage from carrier board.
VBAT_IN	79	-	Input	RTC battery-buffer supply voltage.
3.3V	-	10, 12	Output	Internal 3.3V voltage level.
1.8V	39	-	Output	Internal 1.8V voltage level.
1.5V ¹⁾	-	19	Output	Internal 1.5V voltage level.

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Bank	Schematic Name	Voltage	Notes
500	3.3V, VCCO_MIO0_500	3.3V
501	1.8V, VCCO_MIO1_501	1.8V
502	1.5V, VCCO_DDR_502	1.5V
0 Config	3.3V	3.3V
13 HR	VCCO13	1.2V to 3.3V	Supplied by the carrier board.
33 HR	VCCIO33	1.2V to 3.3V	Supplied by the carrier board.
34 HR	VCCIO34	1.2V 25V to 3.3V	Supplied by the carrier board. This FPGA Bank Power must be supplied and is not optional. Minimum Voltage: B34 signals are used for CPLD/FPGA communication and for PG generated by (TPS3805H33DCKR)
35 HR	VCCIO35	1.2V to 3.3V	Supplied by the carrier board.

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Board to Board Connectors

Include Page

	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors	IN:Samtec LSHM	IN:Samtec LSHM

Variants Currently in Production

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RAM

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eMMC

Size

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Temperature

Range

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B2B Connector

Height

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Page properties

hidden	true
id	Comments

Note: Only table was changed, chapter must be updated in case of TRM Style update

Trenz shop TE0720 overview page
English page	German page

Table 21: Module variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.3	6.5	V	EP53F8QI datasheet.
3.3VIN supply voltage	-0.1	3.75	V	TPS27082L and LCMXO2-1200HC datasheets.
Supply voltage for PS MIO banks	-0.5	3.6	V	See Xilinx DS187 datasheet.
I/O input voltage for MIO banks	-0.4	VCCO_MIO + 0.55	V	See Xilinx DS187 datasheet. (VCCO_MIO0_500, VCCO_MIO1_501)
Supply voltage for HR I/Os banks	-0.5	3.6	V	See Xilinx DS187 datasheet. (VCCIO13, VCCIO33, VCCIO34, VCCIO35)
I/O input voltage for HR I/O banks	-0.4	VCCIO + 0.55	V	See Xilinx DS187 datasheet.
Storage temperature	-40	+85	°C	-
Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed	-55	+100	°C	NB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C.

Table 22: Module absolute maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Note
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	2.5	5.5	V	EN6347QI and EP53F8QI datasheets.
3.3VIN supply voltage	3.135	3.465	V	3.3V +/- 5%

Table 21: Module variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.36.5

V

EP53F8QI datasheet.3.3VIN supply voltage-0.13.75VTPS27082L and LCMXO2-1200HC datasheets

.

Supply voltage for PS MIO banks

-0

1.

5

71

3.

6

465	V	See Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks	-0.

4

20	VCCO_MIO + 0.

55

20

V

See Xilinx DS187 datasheet.

(VCCO_MIO0_500, VCCO_MIO1_501)

Supply voltage for HR I/Os banks

1.14

3.465

Supply voltage for HR I/Os banks-0.53.6

V

See Xilinx DS187 datasheet.

(VCCIO13, VCCIO33, VCCIO34, VCCIO35)

I/O input voltage for HR I/O banks

-0.

4

20	VCCIO + 0.

55

20

V

See Xilinx DS187 datasheet.

Storage temperature

-40

+85

°C

-Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed-55+100°CNB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C.

Table 22: Module absolute and maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Note
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings.

Recommended Operating Conditions

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Table 23: Recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Image Added Image Added

Figure 5: TE0720 module physical dimensions.

Revision History

Hardware Revision History

Date	Revision	Notes	Documentation Link
2015-10-12	03		TE0720-03
-	02		TE0720-02
-	01	Prototypes

Table 24: Hardware revision history table.

There is no hardware revision number marking on the module PCB.

Document Change History

Date

Revision

Contributors

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat

changed currently available chapter to new style

2021-06-21

v.93

Mohsen Chamanbaz

fix typo for LED location on main component section

2019-02-05

v.92

John Hartfiel

small document update

2018-07-05

v.89

John Hartfiel

Update power rail section

2017-11-10

v.85

John Hartfiel

Replace B2B connector section

2017-09-07

v.84

John Hartfiel

Correction of Boot Mode section

2017-08-31

v.83

Jan Kumann

Initial document.

--

all

Page info

infoType	Modified users
type	Flat

--

Table 23: Recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Image Removed Image Removed

Figure 5: TE0720 modules physical dimensions

Weight

ca 23 g - Plain module

Revision History

Hardware Revision History

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Notes

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01

...

Prototypes

...

Table 24: Hardware revision history table.

There is no hardware revision number marking on the module.

Document Change History

Date	Revision	Contributors	Description
2017-08-01	Jan Kumann	Initial document.

Table 25: Document change history table.

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 74

New Version Current

Key

Overview

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Boot Process

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

System Controller CPLD I/O Pins

Boot Process

On-board Peripherals

System Controller CPLD

On-board Peripherals

System Controller CPLD

DDR Memory

Quad SPI Flash Memory

Oscillators

eCompass module

Oscillators

Power-On Sequence

Board to Board Connectors

Variants Currently in Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Operating Temperature Ranges

Physical Dimensions

Weight

Revision History

Hardware Revision History

Document Change History