Page History
...
| HTML |
|---|
<!-- Template Revision 1.4 beta --> |
| Scroll Ignore |
|---|
| Scroll pdf ignore | |
|---|---|
Table of Contents
|
...
- Xilinx Zynq XC7Z SoC, U5
- 4 Gbit DDR3/L SDRAM, U13
- 4 Gbit DDR3/L SDRAM, U12
- Low-power RTC with battery backed SRAM, U20
- 32 MByte Quad SPI Flash memory, U7
- Red LED (LED1LED2), D5
- Green LED (LED2LED1), D2
- System Controller CPLD, U19
- eMMC NAND Flash, U15
- 4A high-efficiency PowerSoC DC-DC step-down converter (1V), U1
- Green LED (DONE), D4
- B2B connector Samtec Razor Beam™ LSHM-130, JM3
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- Hi-speed USB 2.0 ULPI transceiver, U18
- Gigabit Ethernet (GbE) transceiver, U8
- Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
- Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
- Low-dropout regulator (VBATT), U24
- DDR termination regulator, U4
- 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
- Atmel CryptoAuthentication chip, U10
- 2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
- Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
- 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
- 3A PFET load switch with configurable slew rate (3.3V), Q1
...
It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
Use 3.3V or 1.8V output to enable external power supplies or power switches which are used to supply FPGA banks.
See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.
...
Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| 500 | 3.3V, VCCO_MIO0_500 | 3.3V | |
| 501 | 1.8V, VCCO_MIO1_501 | 1.8V | |
| 502 | 1.5V, VCCO_DDR_502 | 1.5V | |
| 0 Config | 3.3V | 3.3V | |
| 13 HR | VCCO13 | 1.2V to 3.3V | Supplied by the carrier board. |
| 33 HR | VCCIO33 | 1.2V to 3.3V | Supplied by the carrier board. |
| 34 HR | VCCIO34 | 1.2V 25V to 3.3V | Supplied by the carrier board. |
| 35 HR | VCCIO35 | 1.2V to 3.3V | Supplied by the carrier board. |
...
Variants Currently in Production
...
| Page properties |
|---|
...
|
...
|
...
| ||
| Note: Only table was changed, chapter must be updated in case of TRM Style update |
| Trenz shop TE0720 overview page | |
|---|---|
| English page | German page |
Size
Temperature
Range
B2B Connector
Height
Table 21: Module variants currently in production.
...
There is no hardware revision number marking on the module PCB.
Document Change History
History
Date | Revision | Contributors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
|
| ||||||||||||||||||||||
| 2021-06-21 | v.93 | Mohsen Chamanbaz |
| ||||||||||||||||||||||
| 2019-02-05 | v.92 | John Hartfiel |
| ||||||||||||||||||||||
2018-07-05 | v.89 | ||||||||||||||||||||||||
Date | Revision | Contributors | Description | ||||||||||||||||||||||
| Page info | | modified-date | modified-date | dateFormat | yyyy-MM-ddJohn Hartfiel |
| |||||||||||||||||||
| 2017-11-10 | v.85 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-09-07 | v.84 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-08-31 | v.83 | Jan Kumann |
| ||||||||||||||||||||||
-- | all |
|
|
Table 25: Document change history table.
...
Overview
Content Tools