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BankTypeConnectorI/O Signal CountVoltageNotes
34HRJ183.3VSignal Schematic names: 'SCL', 'SDA', 'D8' ... 'D13'.
34HRJ283.3VSignal Schematic names: 'RXD', 'TXD', 'D2' ... 'D7'.
34HRJ683.3VSignal Schematic names: 'PIO01' ... 'PIO08'.
34HRJ1113.3VSignal Schematic name: 'AIN_FPGA'.

Signal Schematic names: 'AIN0' ... 'AIN5', usable as single ended of differential analog input inputs or regular digital I/O's.

35HRJ513.3VConnector dedicated to ESP8266 module.
500MIOJ1073.3VSDIO interface to SD Card socket.
 501MIOJ543.3VConnector dedicated to ESP8266 module  .

Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals


BankTypeVCCIOI/O Signal CountAvailable on ConnectorsNotes
34HR3.3V44258 user I/O's on Pmod connector J6, female pin header J1 and J2 each. 1 I/O on pin header J11.
35HR3.3V876 user I/O's on female pin header J4, 1 user I/O on female pin header J5.
500PS MIO3.3V15-6 MIO pins used for QSPI flash memory interface, 7 MIO pins used for SD Card interface, 1 MIO pin connected to red LED D2,
1 MIO pin as reset pin routed to USB PHY U18, 'POR_B'-signal is connected to voltage monitor circuit 23.
501PS MIO3.3V16412 MIO pins used for USB ULPI interface, 4 MIO pins used for ESP8266 interface header J5.
0Config3.3V54-4 I/O's are dedicated to JTAG interface, 'PROG_B'-signal is connected to voltage monitor circuit 23.

Table 3: General overview of Zynq SoC PL/PS I/O bank


ButtonSignal Schematic NameConnected toNotes
S1'NRST'Voltage Monitor Circuit, U23Triggers system reset.


Figure 6: TE0723 board hardware revision number

Document Change History





Page info

Ali Naseri,
Jan Kumann

  • First TRM release

Table 25: Document change history.