Page History

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Bank	Type	Connector	I/O Signal Count	Voltage	Notes
34	HR	J1	8	3.3V	Signal Schematic names: 'SCL', 'SDA', 'D8' ... 'D13'.
34	HR	J2	8	3.3V	Signal Schematic names: 'RXD', 'TXD', 'D2' ... 'D7'.
34	HR	J6	8	3.3V	Signal Schematic names: 'PIO01' ... 'PIO08'.
34	HR	J11	1	3.3V	Signal Schematic name: 'AIN_FPGA'.
35	HR	J4	6	3.3V	Signal Schematic names: 'AIN0' ... 'AIN5', usable as single ended of differential analog input inputs or regular digital I/O's.
35	HR	J5	1	3.3V	Connector dedicated to ESP8266 module.
500	MIO	J10	7	3.3V	SDIO interface to SD Card socket.
501	MIO	J5	4	3.3V	Connector dedicated to ESP8266 module .

Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals

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Bank	Type	VCCIO	I/O Signal Count	Available on Connectors	Notes
34	HR	3.3V	44	25	8 user I/O's on Pmod connector J6, female pin header J1 and J2 each. 1 I/O on pin header J11.
35	HR	3.3V	8	7	6 user I/O's on female pin header J4, 1 user I/O on female pin header J5.
500	PS MIO	3.3V	15	-	6 MIO pins used for QSPI flash memory interface, 7 MIO pins used for SD Card interface, 1 MIO pin connected to red LED D2, 1 MIO pin as reset pin routed to USB PHY U18, 'POR_B'-signal is connected to voltage monitor circuit 23.
501	PS MIO	3.3V	16	4	12 MIO pins used for USB ULPI interface, 4 MIO pins used for ESP8266 interface header J5.
0	Config	3.3V	54	-	4 I/O's are dedicated to JTAG interface, 'PROG_B'-signal is connected to voltage monitor circuit 23.

Table 3: General overview of Zynq SoC PL/PS I/O bank

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Button	Signal Schematic Name	Connected to	Notes
S1	'NRST'	Voltage Monitor Circuit, U23	Triggers system reset.

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Figure 6: TE0723 board hardware revision number

Date

Revision

Contributors

Description

Page info

Ali Naseri,
Jan Kumann

Table 25: Document change history.

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