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Refer to httpshttp://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TEBF0808/REV04 for downloadableorg/tebf0808-info for the current online version of this manual and additionalother technicalavailable documentation of the product.
 

The Trenz Electronic TEBF0808 carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes. The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, MGT interfaces and connectors are accessible, for the front panel elements there are also Intel-PC compatible headers available. 

...

  • Mini-ITX form factor, PC enclosure compatible
  • ATX-24 power supply connector
  • Optional 12V standard power plug
  • Headers
    • Intel 10-pin HDA Audio
    • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
    • PC-BEEPER
  • On-board Power- / Reset-Switches
  • 2x Configuration 4-bit DIP-switches
  • 2x Optional 4-wire PWM fan connectors
  • PCIe Slot - one PCIe lane (16 lane connector)
  • CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
  • 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
  • Dual SFP+ Connector (2x1 Cage)
  • 1x DisplayPort (single lane)
  • 1x SATA Connector
  • 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
  • 1x USB3.0 on-board connector with two ports
  • FMC HPC Slot (FMC_VADJ max. VCCIO)
  • FMC Fan
  • Gigabit Ethernet RGMII PHY with RJ45 MegJackMagJack
  • All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
  • Quad programmable PLL clock generator SI5338A
  • 2x SMA coaxial connectors for clock signals
  • MicroSD- / MMC-Card Socket (bootable)
  • 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
  • 2x System Controller CPLDs Lattice MachXO2 1200 HC
  • 1x Samtec FireFly (4 GT lanes bidirectional)
  • 1x Samtec FireFly connector for reverse loopback
  • 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
  • 20-pin ARM JTAG Connector (PS JTAG0)
  • 3x PMOD connector (GPIO's and I²C interface to SC CPLDs and MPSoC module)
  • On-board DC-DC PowerSoCs

...

On-board PeripheralB2BMPSoC Unit /
SoM peripheral
DescriptionTRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)J1PL Bank (FMC_VADJ)

PL I/O-bank pins, differential pairs

FMC HPC Connector
FMC HPC J5, GTH InterfaceJ1MGT Bank10 MGT LanesFMC HPC Connector
SFP+ 2x1 Cage J14J1MGT Bank2 MGT Lanes to dual SFP+ ConnectorMGT Interfaces SFP+ and FireFly
SMA Coax J33J1On-module PLLSMA Coaxial Connector to on-module
PLL Clock Input pin
Programmable PLL Clock Generator
FMC HPC J5
  • 10 LVDS pairs (20 I/O's)
  • 1 LVDS Clock to PL Bank
  • 2 MGT Clocks to MGT Banks
J2

PL Bank (FMC_VADJ)

MGT Bank

PL I/O-bank pins, differential pairs

1 clock capable PL bank pin-pair

2 MGT clock input pin-pairs

FMC HPC Connector 
Programmable PLL Clock Generator

24-bit Audio Codec U3J3PL Bank (1.8 V)PL I/O-bank pins to on-board
24-bit Audio Codec
Intel-PC Compatible Headers and FAN Connectors
24-bit Audio Codec
10 I/O's to SC CPLD U17J3PL Bank (1.8 V)

PL I/O-bank pins to on-board
System Controller CPLD U17

System Controller CPDLsCPLDs
8 I/O's to SC CPLD U39J3PL Bank (1.8 V)

PL I/O-bank pins to on-board
System Controller CPLD U39

System Controller CPDLsCPLDs
SDIO Interface, SD- / MMC-Card MuxJ3PS MIOSDIO interface connected to
SD- / MMC-Card socket
MIO Bank Interfaces
SDIO Port Expander
Board Peripheral's I²C Interfaces
muxed to MPSoC I²C
J3PS MIOMPSoC I²C interface configured as
master connected to on-board slaves
MIO Bank Interfaces 
8-Channel I²C Switches
4 MIO to SC CPLD U17J3PS MIOFunctionality depending on MPSoC and
CPLD firmware
System Controller CPDLsCPLDs
15 MIO to SC CPLD U39J3PS MIO

Functionality depending on MPSoC and
CPLD firmware

System Controller CPDLs
Ethernet PHY RGMIIJ3PS MIOEthernet PHY U12 connected per RGMII

MIO Bank Interfaces
Gigabit Ethernet PHY

eMMC FlashJ3PS MIOeMMC Flash memory interface on PS bankMIO Bank Interfaces 
eMMC Memory
USB2.0 PHY ULPIJ2PS MIOUSB2.0 PHY U9 connected per ULPIMIO Bank Interfaces
High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15J2MGT BankMGT Lanes to Samtec FireFly connectorMGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12J2PS ConfigMPSoC USB programmable JTAG interface

MIO Bank Interfaces
JTAG Interface

USB3.0 LaneJ2PSGTUSB3.0 PS MGT Lane

MIO Bank Interfaces
PS GT Bank Interfaces

4-port USB3.0 Hub--USB3.0 (2.0 compatible) Hub with 4 portsMIO Bank Interfaces
4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7,
USB3.0 Connector J8
--2-port USB3.0 / RJ45 GbE Connector (stacked)MIO Bank Interfaces
25 SoM Control Signals to
SC CPLDs U17 / U39
J2On-module DC-DC
converter, PLL clock
generator
Control Signals, e.g.  "Enable"- / "Power Good"-
signals of DC-DC-converter and further on-module
peripherals

Power-On Sequence Diagram
Programmable PLL Clock Generator

150 MHz Osci Clock InputJ2-150 MHz SATA interface MGT clockOscillators

Signals DONE, INIT_B, SRST_B, ...
to SC CPLD U39

J2PS ConfigMPSoC control signal for PS- / PL configurationSystem Controller CPDLsCPLDs

SATA Connector J31
PCIe Connector J1
DisplayPort J13

J2PSGTConnectors of the MGT based data interfacesPS GT Bank Interfaces

PLL Clock Output to

  • PCIe Interface
  • On-board PLL U35
  • MGT Bank (B2B J3)
J2On-module PLL
clock generator

Reference clock signals of the on-module
programmable PLL clock generator

Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33J4PL Bank (FMC_VADJ)PL user I/O's accessible on PMOD connector P2CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32J4PL Bank (FMC_VADJ)PL user I/O's routed to System Controller
CPLD U17
System Controller CPDLsCPLDs
FMC HPC J5
  • 46 LVDS pairs (92 I/O's)
  • 1 LVDS Clock to PL Bank
J4PL Bank (FMC_VADJ)

PL I/O-bank pins, differential pairs

1 clock capable PL bank pin-pair

FMC HPC Connector
Programmable PLL Clock Generator

...

The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

4 lanes, pins J5-A10, J5-A11, pins J5-A30, J5-A31, pins J5-A6, J5-A7, pins J5-A26, J5-A27, pins J5-A2, J5-A3, pins J5-A22, J5-A23, pins J5-C6, J5-C7 J5C2 J5-C3
B2BCount Schematic Names of the MGT LanesSignalsSchematic Names / B2B Connector PinsMGT Bank's Reference Clock Inputs from FMC Connector J1Pins

B228_RX3_P, B228_RX3_N


B228_TX3_P, B228_TX3_N

B228_RX2_P, B228_RX2_N


B228_TX2_P, B228_TX2_N

B228_RX1_P, B228_RX1_N


B228_TX1_P, B228_TX1_N

B228_RX0_P, B228_RX0_N


B228_TX0_P, B228_TX0_N

pins J1-51, J1-53
pins

J1-

50,

1 MGT clock (B228_CLK0) from FMC connector
J5 (pins J5-D4, J5-D5) to MPSoC's MGT bank

J14 lanes

B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13
B229_TX3_P, B229_TX3_N, pins J5-B32, J5-B33

B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17
B229_TX2_P, B229_TX2_N, pins J5-B36, J5-B37

B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19
B229_TX1_P, B229_TX1_N, pins J5-A38, J5-A39

B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15
B229_TX0_P, B229_TX0_N, pins J5-A34, J5-A35

1 MGT clock (B229_CLK0) from FMC connector
J5 (pins J5-B20, J5-B21) to MPSoC's MGT bank

J12 lanes

B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5
B230_TX1_P, B230_TX1_N, pins J5-B24, J5-B25

B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9
B230_TX0_P, B230_TX0_N, pins J5-B28, J5-B29

-

...

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

...

The FMC connector provides further interfaces like JTAG and I²C interfaces:

...

FMC_TCK, pin J5-D29

FMC_TMS, pin J5-D33

FMC_TDI, pin J5-D30

FMC_TDO, pin J5- D31

...

VCCIO: 3V3SB

TRST_L, pin J5-D34 pulled-up to 3V3_PER

...

FMC_SCL, pin J5-C30

FMC_SDA, pin J5-C31

...

I²C-lines pulled-up to 3V3_PER

...

FMC_PRSNT_M2C, pin J5-H2

FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up)

FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up)

FMC_CLK_DIR, pin J5-B1 (pulled-down to GND)

...

I²C I/O Expander U38

SC CPLD U39, bank 0

I²C I/O Expander U38

SC CPLD U17, bank 1

...

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier

J1-52

pins J1-57, J1-59
pins J1-56, J1-58

pins J1-63, J1-65
pins J1-62, J1-64

pins J1-69, J1-71
pins J1-68, J1-70

pins J5-A10, J5-A11
pins J5-A30, J5-A31

pins J5-A6, J5-A7
pins J5-A26, J5-A27

pins J5-A2, J5-A3
pins J5-A22, J5-A23

pins J5-C6, J5-C7
pins J5-C2, J5-C3

B229_RX3_P, B229_RX3_N
B229_TX3_P, B229_TX3_N

B229_RX2_P, B229_RX2_N
B229_TX2_P, B229_TX2_N

B229_RX1_P, B229_RX1_N
B229_TX1_P, B229_TX1_N

B229_RX0_P, B229_RX0_N
B229_TX0_P, B229_TX0_N

pins J1-27, J1-29
pins J1-26, J1-28

pins J1-33, J1-35
pins J1-32, J1-34

pins J1-39, J1-41
pins J1-38, J1-40

pins J1-45, J1-47
pins J1-44, J1-46

pins J5-B12, J5-B13
pins J5-B32, J5-B33

pins J5-B16, J5-B17
pins J5-B36, J5-B37

pins J5-A18, J5-A19
pins J5-A38, J5-A39

pins J5-A14, J5-A15
pins J5-A34, J5-A35

B230_RX1_P, B230_RX1_N
B230_TX1_P, B230_TX1_N

B230_RX0_P, B230_RX0_N
B230_TX0_P, B230_TX0_N

pins J1-15, J1-17
pins J1-14, J1-16

pins J1-21, J1-23
pins J1-20, J1-22

pins J5-B4, J5-B5
pins J5-B24, J5-B25

pins J5-B8, J5-B9
pins J5-B28, J5-B29

Table 4: FMC connector pin-outs of available MGT lanes of the MPSoC

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

Clock Signal Schematic Name
FMC Connector PinsDirectionClock SourceNotes
B228_CLK0J5-D4 / J5-D5inFMC Connector J5Extern MGT clock
B229_CLK0J5-B20 / J5-B21inFMC Connector J5Extern MGT clock
FMCCLK2J5-K4 / J5-K5outCarrier Board PLL SI5338A U35, CLK2Clock signal to Mezzanine module
FMCCLK3J5-J2 / J5-J3outCarrier Board PLL SI5338A U35, CLK3Clock signal to Mezzanine module
B64_L14_P / B64_L14_NJ5-H4 / J5-H5inFMC Connector J5Extern LVDS clock to PL bank
B48_L6_P / B48_L6_NJ5-G2 / J5-G3inFMC Connector J5Extern LVDS clock to PL bank

Table 5: FMC connector pin-outs for reference clock output

The FMC connector provides further interfaces like JTAG and I²C interfaces:

Interfaces I/O Signal CountPin schematic Names / FMC PinsConnected toNotes
JTAG5

FMC_TCK, pin J5-D29

FMC_TMS, pin J5-D33

FMC_TDI, pin J5-D30

FMC_TDO, pin J5- D31

SC CPLD U17, bank 1

VCCIO: 3V3SB

TRST_L, pin J5-D34 pulled-up to 3V3_PER

I²C2

FMC_SCL, pin J5-C30

FMC_SDA, pin J5-C31

I²C Switch U16

I²C-lines pulled-up to 3V3_PER

Control Lines4FMC_PRSNT_M2C, pin J5-H2I²C I/O Expander U38

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier

FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up)SC CPLD U39, bank 0
FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up)I²C I/O Expander U38
FMC_CLK_DIR, pin J5-B1 (pulled-down to GND)SC CPLD U17, bank 1

Table 6: FMC connector pin-outs of available interfaces to the System Controller CPLD

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

VCCIO Schematic NameFMC Connector J5 PinsNotes
12VC35/C37extern 12V power supply
3V3_PERD32/D36/D38/D40/C393.3V peripheral supply voltage
FMC_VADJH40/G39/F40/E39adjustable FMC VCCIO voltage, supplied by DC-DC converter U8

Table 7:  Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

MIOConfigured asSystem Controller CPLDNotes
0..12Dual QSPI-Dual Flash Memory on TE0808 / TE0803 SoM; Bootable
13..23SD0: eMMC-eMMC Memory U2; Bootable
24, 25-CPLD (U39) MUXED-
26..29-CPLD (U17 MUXEDBootable JTAG (PJTAG0)
30force reboot after FSBL-PLL config for PCIeCPLD (U39) MUXED-
31PCIe resetCPLD (U39) MUXED-
32-CPLD (U39) MUXED-
33-CPLD (U39) MUXED-
34..37-CPLD (U39) MUXED-
38, 39I2C0--
40forwarded to PWRLED_P / LED_PCPLD (U39) MUXED-
41---
42, 43UART0CPLD (U39) MUXED-
44SD_WP to FPGA CPLD (U39) MUXED-
45..51SD1: SD-Bootable MikroSD / MMC Card
52..63USB0--
64..75GEM3-Ethernet RGMII
76, 77MDC / MDIO -Ethernet RGMII

Table 8:  MIO Assignment

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

  • 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
  • SDIO port with muxed MikroSD and MMC Card socket
  • Gigabit Ethernet interface connected per RGMII
  • eMMC interface
  • Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Added

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

  • SATA (PS GT bank, MGT2 Lane)
  • DisplayPort (PS GT bank, MGT3 Lane, only TX-pair routed)
  • PCI Express (PS GT bank, MGT0 Lane)

FunctionMGT LaneSchematic Names / B2B pinsRequired Ref ClockClock SourceComment
PCIePS 0

PCI_TX_N, pin J2-67
PCI_TX_P, pin J2-69

PCI_RX_N, pin J2-70
PCI_RX_P, pin J2-72

100 MHzclock signal of SoM's prog. PLL

single lane PCIe connector

clock signal routed on carrier board to PCIe connector J1

USB3PS 1

USB3_TXUP_N, pin J2-61
USB3_TXUP_P, pin J2-63

USB3_RXUP_N, pin J2-64
USB3_RXUP_P, pin J2-66

100 MHzclock signal of SoM's prog. PLL

clock signal routed on-module,
Optional (not equipped) 100 MHz osci. U6 is possible (Configurable on Zynq PS).

SATAPS 2

SATA_TX_N, pin J2-55
SATA_TX_P, pin J2-57

SATA_RX_N, pin J2-58
SATA_RX_P, pin J2-60

150 MHzOn-board oscillator U23

optional: clock signal of SoM's prog. PLL

DP.0PS 3

DP0_TX_N, pin J2-49
DP0_TX_P, pin J2-51

27 MHzclock signal of SoM's prog. PLL

DisplayPort GT SERDES clock signal,
routed on-module to MGT bank

Table 9:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Added

Figure 5: TEBF0808 PS GT Bank 505 Interface

Follwowing table contains a brief description of the control and status signals of PCIe interface:

Signal Schematic NameFPGA DirectionDescriptionLogic
WAKEInputLink reactivationLow active
PERSTInputPCI Express reset inputLow active
PRSNT1InputReference pin for PCIe card lane size-
PRSNT2InputPCI Express ×1 cardsconnect to PRSNT1
PRSNT3InputPCI Express ×4 cardsconnect to PRSNT1
PRSNT4InputPCI Express ×8 cardsconnect to PRSNT1
PRSNT5InputPCI Express ×16 cardsconnect to PRSNT1
PCIE_I²CBiDir2-wire PCIE System Management Bus-

Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

FunctionMGT LaneSchematic Names / B2B pinsRequired Ref ClockClock SourceComment
FireFlyMGT Lanes 0..3

B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

...

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

...

Table 7:  Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

...

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

  • 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
  • SDIO port with muxed MikroSD and MMC Card socket
  • Gigabit Ethernet interface connected per RGMII
  • eMMC interface
  • Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Removed

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

...

single lane PCIe connector

clock signal routed on carrier board to PCIe connector J1

...

clock signal routed on-module,
also optional (not equipped) 100 MHz osci. U35 configurable

...

optional: clock signal of SoM's prog. PLL

...

DisplayPort GT SERDES clock signal,
routed on-module to MGT bank

Table 9:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Removed

...

Follwowing table contains a brief description of the control and status signals of PCIe interface:

...

Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

FunctionMGT LaneRequired Ref ClockClock SourceComment
FireFlyMGT Lanes 0..3

-clock signal of SoM's prog. PLLclock signal on-module routed to MGT bankon-module routed to MGT bank
SFPMGT Lane 2

B230_RX2_P, pin J1-9
B230_RX2_N, pin J1-11

B230_TX2_P, pin J1-8
B230_TX2_N, pin J1-10

SFPMGT Lane 2

125 / 156.25 MHzclock signal of SoM's prog. PLLclock signal routed on carrier board to MGT bank
SFPMGT Lane 3

B230_RX3_P, pin J1-3
B230_RX3_N, pin J1-5

B230_TX3_P, pin J1-2
B230_TX3_N, pin J1-4

125 / 156.25 MHzclock signal of SoM's prog. PLLclock signal routed on carrier board to MGT bank

...

PMODInterfaceConnected toNotes
P1I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface through I²C switch U27
P2GPIOHP Bank of MPSoC (4 I/O's, B65_T0 ... B65_T3),
System Controller CPLD U17 (4 I/O's, EX_IO1 ... EX_IO4)
Voltage translation via IC U33 with direction control,
only singled-ended signaling possible
P2I²C8-channel I²C Switch U27
only singled-ended signaling possibleAccessible on MPSoC's I²C interface through I²C switch U27
P3I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface through I²C switch U27

...

The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 89. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

...

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller

...

CPLDs

The TEBF0808 is equipped with two System Controller CPLDs - Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family) - with the schematic designators U17 and U39.

...

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both Sytem System Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

...

Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U10USB0_RCLK52.000000 MHzUSB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13ETH_CLK25.000000 MHzGigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7-25.000000 MHzQuad PLL clock generator U35, pin 3
DSC1123 oscillator, U23B505_CLK1150.0000 MHzPS GT Bank, dedicated for SATA interface

DSC1123 oscillator, U6

optional, not equipped

B505_CLK0100.0000 MHzPS GT Bank, dedicated for USB interface

Silicon Labs 570FBB000290DG, U45

optional, not equipped

B47_L5 (LVDS)250.MHzPL Bank clock capable input pins
SiTime SiT8008BI oscillator, U25CLK_CPLD2524.576000 MHzSystem Controller CPLD U35, pin 128

...

I²C Slave Devices connected to MPSoC I²C InterfaceI²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
8-channel I²C switch U16-0x73I2C_SDA / I2C_SCL
8-channel I²C switch U27-0x77I2C_SDA / I2C_SCL
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL)-User programmableI2C_SDA / I2C_SCL
I²C Slave Devices connected to 8-channel I²C Switch U16I²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
On-board Quad programmable PLL clock generator U35 Si533800x70MCLK_SDA / MCLK_SCL
8-bit I²C IO Expander U4410x26SFP_SDA / SFP_SCL
PCIe Connector J12module dependentPCIE_SDA / PCIE_SCL
SFP+ Connector J14A3module dependentSFP1_SDA / SFP1_SCL
SFP+ Connector J14B4module dependentSFP2_SDA / SFP2_SCL
Configuration EEPROM U24U4250x54MEM_SDA / MEM_SCL
Configuration EEPROM U3650x52MEM_SDA / MEM_SCL
Configuration EEPROM U4150x51MEM_SDA / MEM_SCL
Configuration EEPROM U2250x50MEM_SDA / MEM_SCL
8-bit I²C IO Expander U3850x27MEM_SDA / MEM_SCL
FMC Connector J56module dependentFMC_SDA / FMC_SCL
USB3.0 Hub configuration EEPROM U570x51USBH_SDA / USBH_SCL
USB3.0 Hub70x60USBH_SDA / USBH_SCL
I²C Slave Devices connected to 8-channel I²C Switch U27I²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
PMOD Connector P10module dependentPMOD_SDA / PMOD_SCL
24-bit Audio Codec U310x38A_I2C_SDA / A_I2C_SCL
FireFly Connector J152module dependentFFA_SDA / FFA_SCL
FireFly Connector J223module dependentFFB_SDA / FFB_SCL
On-module Quad programmable PLL clock generator Si5345 (TE0808)40x69PLL_SDA / PLL_SCL
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL)5User programmableSC_SDA / SC_SCL
8-bit I²C IO Expander U3460x24FF_E_SDA / FF_E_SCL
PMOD Connector P37module dependentEXT_SDA / EXT_SCL

...

EEPROM ModellSchematic DesignatorMemory DensityPurpose
24LC128-I/STU24U30128 Kbituser
24AA025E48T-I/OTU362 Kbituser
24AA025E48T-I/OTU412 Kbituser
24AA025E48T-I/OTU422 Kbituser
24LC128-I/STU5128 KbitUSB3.0 Hub U4 configuration memory

Table 21:  On-board configuration EEPROMs overview

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic).

DIP-Switches

There are two 4 bit DIP Switches on the TEBF0808 carrier board to configure options and set parameters. The table below describes the functionalities of the particular switches:

...

-I/OTU422 Kbituser
24LC128-I/STU5128 KbitUSB3.0 Hub U4 configuration memory

Table 21:  On-board configuration EEPROMs overview

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic).

DIP-Switches

There are two 4-bit DIP-witches present on the TEBF0808 carrier board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-switch S4

Table below describes the functionalities of the switches of DIP-switch S4 at their single positions:

DIP-switch S4Position ONPosition OFFNotes
S4-1PUDC_B is LowPUDC_B is HIGHInternal pull-up resistors during configuration are enabled at ON-position,
means I/O's are 3-stated until configuration of the FPGA completes. 
S4-2xxnot connected
S4-3SC CPLDs' JTAG enabledSC CPLDs' JTAG disabledJTAG interface is enabled on both SC CPLDs, as this CPLDs are
configured in a casdaced JTAG chain.
S4-4DC-DC converter U18 (5V) enabledDC-DC converter U18 (5V) not manually enabledIn OFF-position, the DC-DC-converter will be still enabled by the
Enable-signal ('5V_EN') of SC CDPD U39 (wired-OR circuit).

Table 22: DIP-switch S4 functionality description

DIP-switch S5

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The DIP-switch is connected to SC CPLD U17 and U39 as fellows:

DIP-switch S5Signal Schematic NameConnected toFunctionalityCPLD Documentation
S5-1SC_SW1SC CPLD U39, pin 133set 2-bit code for boot mode selection

TEBF0808 Slave CPLD

Section: Boot Mode

S5-2SC_SW2SC CPLD U39, pin 138
S5-3SC_SW3SC CPLD U17, pin 6user defined

TEBF0808 Master CPLD

S5-4SC_SW4SC CPLD U17, pin 5set FMC_VADJ: 1.8V at ON-position, 1.2V at OFF-position

Table 23: DIP-switch S5 connection to SC CPLDs


The boot mode of the mounted Ultrascale+ Zynq MPSoC module will be set in current SC CPLD U39 firmware version as described in the table below:

S5-1S5-2Description

...

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The switches of this DIP-switch have to be set in bit-patterns to set a parameter like boot mode or FMC_VADJ value:

ONxxx
S5-1S5-2S5-3S5-4Description
ON
ONONDefault, boot from SD/eMMC, 1.8V FMC VADJONONxxBoot from microSD , SD or SPI Flash if no SD is detected
OFFONxBoot from eMMC
ONOFFxBoot mode  PJTAG0
OFFOFFxBoot mode main  JTAG
xxxONFMC VADJ = 1.8V
xxxOFFFMC VADJ = 1.2V

Table 23: DIP-switch S4 functionality descriptionS5 boot mode selection

On-board LEDs

The TEBF0808 carrier board is equipped with several LED to signal current states and activities. The functionality of the LEDs D4 ... D7 depends on the current firmware of the SC CPLDs U17 and U39.

...

 Figure 12: Power Distribution Diagram

Note

Current rating of  Samtec Razor Beam™ LSHM Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 21.0A 5 A per pin (2 adjacent pins powered1 pin powered per row).

Power-On Sequence Diagram

...

Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U39, which enables the particular on-board voltages. 


Figure 13: Power-On Sequence Utilizing DCDC Converter Control Signals

Note

As shown in Figure 1213, the DIP switch S4-4 has to be closed if using only 12V single power supply through 12V power jack J25, otherwise the 5V voltage level will not be enabled to generate the 3V3SB voltage to power up the SC CPLD U39 and starting the power-on sequence.
By using an ATX-24 power connector on J20, there is usually also a 5V supply voltage provided, hence the DIP switch S4-4 is not relevant in this case of power supply.

...

J22PER 1, 10
Peripheral DesignatorVCC / VCCIODirectionPinsNotes
J233.3VSBOutPin 1PC Compatible BEEPER
J11

12V

Out

Pin A2, A3, B1, B2, B3

PCIe Connector
3.3V_PCIOut

Pin A9, A10, B8, B10

-

J295VOutPin 5CAN-Bus Header
J13DP_TX_PWROutPin 20Display-Port Connector
J14A3.3V_PCIOutPin T15, T16SFP+ 2x1 Connector
J14B3.3V_PCIOutPin L15, L16SFP+ 2x1 Connector
J153.3V_PEROutPin 1, 10FireFly Connector
J223.3V_PEROutPin 1, 10FireFly ConnectorConnector
J7AVBUS4OutPin U1USB3.0 Connector
J7BVBUS3OutPin U10USB3.0 Connector
J8

VBUS1

OutPin 19USB3.0 Header
VBUS2OutPin 1-
J163.3V_SD_AOutPin 4MicroSD Card Socket
J273.3V_SD_BOutPin FireFly Connector
J7AVBUS4OutPin U1USB3.0 Connector
J7BVBUS3OutPin U10USB3.0 Connector
J8

VBUS1

OutPin 19USB3.0 Header
VBUS2OutPin 1-
J163.3V_SD_AOutPin 4MicroSD Card Socket
J273.3V_SD_BOutPin 4MMC Card Socket
B1VBATTInPin +Battery Holder

Table 32: Power pin description of Peripherals' Connector

B2B connectors

...

4MMC Card Socket
B1VBATTInPin +Battery Holder

Table 32: Power pin description of Peripherals' Connector

B2B connectors

Include Page
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Unit

Notes / Reference Document

Power supply voltage (12V nominal)11.412.6VANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
Battery Voltage VBATT-0.52VXilinx DS925 data sheet
Voltage on pins of PMOD P2-0.53.75VMachXO2 Family Data Sheet

Storage temperature (ambient)

-55

85

°C

Marvell 88E1512 datasheet

Table 33: Board absolute maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

...

Technical Specifications

...

ParameterMinMaxUnitNotes / Reference Document
Power supply voltage (12V nominal)11.412.6VANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
Battery Voltage VBATT-0.52VXilinx DS925 data sheet
Voltage on pins of PMOD P2-0.53.75VMachXO2 Family Data Sheet

Storage temperature (ambient)

-55

85

°C

Marvell 88E1512 datasheet

Table 33: Board absolute maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

...

1.21.5VXilinx DS925 data sheet
Voltage on pins PMOD P23.1353.6VMachXO2 Family Data Sheet

Table 34: Board recommended operating conditions.

Note
Please check TRM TE0808 / TE0803 and Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings for the mounted UltraSoM+.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The carrier board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted UltraSOM+ modules, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

  • Module size: 170 mm × 170 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 5 mm

  • PCB thickness: 1.844 mm ± 10%

  • Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

 Image Added       Image Added

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

 DateRevision

Notes

Link to PCNDocumentation Link
-04Current available board revision-TEBF0808-04
-03Second production release-TEBF0808-03
-02First production release-TEBF0808-02
-01Prototype--

Table 35: Board hardware revision history.

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Added

Figure 15: Board hardware revision number.

Document Change History

 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • System Controller links fixed
2019-09-03v.96Thomas Steffens
  • correction EEPROM Designator
  • correction typ U25 CLK

2018-07-02

v.89Martin Rohrmüller
  • Typo

2018-05-31

v.88

John Hartfiel
  • Typo correction Table 13
  • Typo correction Table 9
2017-11-15v.86Ali Naseri
  • DIP-switches section revised and updated

2017-11-13

v.82

Ali Naseri
  • updated B2B connector max. current rating
    per pin

2017-11-13

v.80

John Hartfiel
  • rework B2B section
2017-10-19

v.79

Ali Naseri
  • added additionally MGT lanes information

2017-10-18

v.75

Table 34: Board recommended operating conditions.

Note
Please check TRM TE0808 / TE0803 and Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings for the mounted UltraSoM+.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The carrier board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted UltraSOM+ modules, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

  • Module size: 170 mm × 170 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 5 mm

  • PCB thickness: 1.844 mm ± 10%

  • Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

 Image Removed       Image Removed

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

...

Notes

...

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Removed

Figure 15: Board hardware revision number.

Document Change History

yyyy-MM-dd
 Date

Revision

ContributorsDescription
Page info
modified-datemodified-datedateFormatAli Naseri
  • added Power Rails section

2017-08-29

v.70



John Hartfiel
  • update document change history
  • published
2017-08-28v.69Ali Naseri
  • Initial document

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --

Table 36: Document change history.

...