Page History
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Storage device name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
EFUSE eFUSE USER | Not programmed | - |
EFUSE eFUSE Security | Not programmed | - |
Signals, Interfaces and Pins
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On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an onboard on-board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
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On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C AdressAddress | Notes |
|---|---|---|
| EEPROM | 0x50 | |
| RTC | 0x6F | |
| Battery backed RAM | 0x57 | Integrated into RTC. |
PLL | 0x70 |
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| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 MhzMHz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 MhzMHz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
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| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 2016-06-21 | 04 | Second production release | Click to see PCN | TE0715-04 |
| - | 03 | First production release | TE0715-03 | |
| - | 02 | Prototypes | ||
| - | 01 | Prototypes |
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2016-11-15 | Thorsten Trenz
| Added B2B Connector section. | |
| 2016-10-18 | V40 | Ali Naseri | Added table "power rails". |
| 2016-06-28 | V38
| Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pinout Pin-out Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. |
| 2016-04-27 | V33 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis | Added the table "Recommended Operating Conditions". Storage Temperature edited. |
| 2016-03-31 | V10 | Philipp Bernhardt, Antti Lukats | Initial version. |
Disclaimer
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