Page History

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Main Component

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1. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
2. Samtec Razor Beam™ LSHM-150 B2B connector, JB3
3. Samtec Razor Beam™ LSHM-130 B2B connector, JB2
4. 6-pin header J26, for selecting PL I/O-bank voltage
5. 6-pin header J27J5, for selecting PL I/O-bank voltage
6. Micro USB2 Type B connector J12 (Device or OTG mode)
7. XMOD FTDI JTAG/UART header, JX1
8. 6-pin header J6, for selecting PL I/O-bank voltage
9. 6-pin header J27, for selecting PL I/O-bank voltage
10. Micro USB2 Type B connector J10 (Device or OTG mode)
11. 2-pin VBAT header J7
12. XMOD FTDI JTAG/UART header, JX1
13. 4-bit DIP-switch S1
14. User User LED D1 (green)
15. User LED D2 (red)
16. SFP+ Connector, J1
17. 5010-pin header soldering-pads J17, for access to PL J4, 6 I/O-bank pins (42 I/O'S, 21 LVDS pairs's available
18. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
19. 50-pin header soldering-pads J20J17, for access to PL I/O-bank pins (42 I/O'S, 21 LVDS pairs)
20. 1650-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)10-pin header soldering-pads J4, 6 I/O's availableJ20, for access to PL I/O-bank pins (42 I/O'S, 21 LVDS pairs)
21. SFP+ Connector, J1

Initial Delivery State

Board is shipped in following configuration:

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Following table gives a summary of the available I/O's, interfaces and differential pairs of the mounted SoM on the B2B connectors JB1, JB2 and JB3 of the carrier board:

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors

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Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors

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Following table describes the pin-assignment of the SFP+ connector:

Table 3: SFP+ connector pin-assignment

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The MGT lane pins are routed on-board as follows, if 4 x 5 SoM TE0841 is mounted on carrier board:

Table 4: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0841

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JTAG access to the mounted SoM is provided through B2B connector JB3 and is routed to the XMOD header JX1 and also to pin header J3. With the TE0790 XMOD USB2 to JTAG adapter, the FPGA device of the mounted SoM can be programed via USB2 interface.

Table 5: JTAG interface signals

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Following table describes the signals and interfaces of the XMOD header JX1:

Table 6: XMOD header JX1 signals and connections

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the XMOD DIP-switch with the setting:

Table 7: XMOD adapter board DIP-switch positions for voltage configuration

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As alternative to the XMOD header JX1, on the carrier board pin header J3 is present, which has a XMOD header-compatible pin-assignment, but also two additional pins (15,16) as differential pair to supply the mounted SoM with an external MGT reference clock signal:

Table 8: JTAG/UART header J3 signals and connections

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UART interface is available on B2B connector JB1 established by the mounted SoM's FPGA device. With the TE0790 XMOD USB2 adapter, the UART signals can be converted to USB2 interface signals:

Table 9: UART interface signals

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Following table gives an overview of the USB2 interface signals:

Table 10: USB2 interface signals and connections

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The on-board LEDs are available to the user and can be used to indicate system status and activities:

Table 11: On-board LEDs

DIP-Switch

There are one 4-bit DIP-witches S1 present on the TEBA0841 board to configure options and set parameters. The following table describes the of the particular switches:

Table 12: DIP-switch S1, see also 4x5 Module Controller IOs

VCCIO Selection Jumper

On the TEBA0841 carrier board different VCCIO configurations can be selected by the jumper header J26, J27, J5 and J6.

TE 4 x 5 Modules have a standard assignment of PL-bank I/O voltages on the B2B connectors, which will be fed with I/O voltage from base-board.

Table 13: Base-board PL-bank I/O voltages VCCIOA ... VCCIOD

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Following table describes how to configure the base-board supply-voltages by jumpers:

Table 14: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 15: Typical power consumption

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The external power-supply can be connected to the board by the following pins:

Table 16: Connector pins capable for external 3.3V power supply

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Power Rails

The voltage direction of the power rails is from board and on-board connectors' view:

Table 17: Power pin description of B2B module connector

Table 18: Power Pin description of on-board connector

Table 19: Power Pin description of VCCIO selection jumper pin header

Table 20: Power pin description of peripheral connector

Table 21: Power pin description of XMOD/JTAG connector

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Technical Specifications

Absolute Maximum Ratings

Table 22: Board absolute maximum ratings

Recommended Operating Conditions

Table 23: Module recommended operating conditions

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Hardware Revision History

Table 24: Module hardware revision history

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Document Change History

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