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| Switch | Signal Name | ON | OFF | Notes |
|---|---|---|---|---|
| S1-1 | - | - | - | Not connected |
| S1-2 | PROGMODE | JTAG enabled for programing SoM FPGA | JTAG enabled for programing SoM CPLD | - |
| S1-3 | MODE | Drive SoM SC CPLD pin 'MODE' low | leave SoM SC CPLD pin 'MODE' open | Boot mode configuration, if supported by SoM. (Depends also on SoM's SC CPLD firmware). |
| S1-4 | EN1 | Drive SoM SC CPLD pin 'EN1' low | drive SoM SC CPLD pin 'EN1' high | Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware). Note: Power-on sequence will be intermitted when S1-4 is set to OFF and functionality is supported by SoM. |
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