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Refer to "https://shop.trenz-electronic.de/deen/Download/?path=Trenz_Electronic/TE0715" for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GB of DDR3 SDRAM, 32MB of SPI flash memory, gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.
Block Diagram
Main Components
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Storage device name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
| Si5338 OTP NVM | Not programmed | Can be pre-programmed for special order only |
Signals, Interfaces and Pins
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| Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
13 | HR | JM1 | 48 | User | Supported voltages from 1.2V to 3.3V. |
34 | HR/HP | JM2 | 18 | User | TE0715-xx-15 has no HP banks, banks 34 and 35 are HR banks on this module! Banks 34 and 35 on TE0715-xx-30 are HP banks and support voltages from 1.2V to 1.8V. |
| 35 | HR/HP | JM2 | 50 | User | As above. |
34 | HR/HP | JM3 | 16 | User | As above. |
500 | MIO | JM1 | 8 | 3.3V | - |
501 | MIO | JM1 | 6 | 1.8V | - |
112 | GT | JM3 | 4 Laneslanes | N/A | - |
112 | GT CLK | JM3 | 1 differential Inputinput | N/A | NB! AC coupling capacitors on baseboard required. |
For detailed information about the pin out, please refer to the Pin-out Table.
Default MIO Mapping
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
JTAG Signal | B2B Connector Pin |
|---|---|
| TMS | JM2-93 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TCK | JM2-99 |
| Note |
|---|
| JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
System Controller I/O Pins
Special purpose pins are connected to System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| EN1 | Input | Power Enable | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset. |
| PGOOD | Output | Power Good | Active high when all on-module power supplies are working properly. |
| NOSEQ | - | - | No function. |
| RESIN | Input | Reset | Active low reset, gated to POR_B. |
| JTAGEN | Input | JTAG Select | Low for normal operation. |
LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D2 | Green | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted). |
Default MIO Mapping
| MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | GPIO | JM1-87 | B2B | 16..27 | ETH0 | - | RGMII | ||||||
| 1 | |||||||||||||
| MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | ||||||
| 0 | GPIO | JM1-87 | B2B | 16..27 | ETH0 | - | RGMII | ||||||
| 1 | QSPI0 | - | SPI Flash-CS | 28..39 | USB0 | - | ULPI | ||||||
| 2 | QSPI0 | - | SPI Flash-DQ0 | 40 | SDIO0 | JM1-27 | B2B | ||||||
| 3 | QSPI0 | - | SPI Flash-DQ1 | 41 | SDIO0 | JM1-25 | B2B | ||||||
| 4 | QSPI0 | - | SPI Flash-DQ2 | 42 | SDIO0 | JM1-23 | B2B | ||||||
| 5 | QSPI0 | - | SPI Flash-DQ3 | 43 | SDIO0 | JM1-21 | B2B | ||||||
| 6 | QSPI0 | - | SPI Flash-SCK | 44 | SDIO0 | JM1-19 | B2B | ||||||
| 7 | GPIO | - | Green LED D4 | 45 | SDIO0 | JM1-17 | B2B | ||||||
| 8 | QSPI0 | - | SPI Flash-SCKFBCS | 46 | 28..39 | USB0GPIO | - | Ethernet PHY LED2 INTn Signal. | ULPI | ||||
| 2 | QSPI0 | - | SPI Flash-DQ0 | 940 | SDIO0 | JM1- | 9127 | B2B | |||||
| 3 | 47QSPI0 | GPIO- | SPI Flash-DQ1 | RTC Interrupt | 1041 | SDIO0 | JM1- | 9525 | B2B | ||||
| 4 | 48QSPI0 | I2C1- | SPI Flash-DQ2 | SCL on-board I2C | 42 | SDIO0 | 11 | JM1- | 9323 | B2B | |||
| 5 | 49QSPI0 | I2C1- | SPI Flash-DQ3 | SDA on-board I2C | 43 | SDIO0 | 12 | JM1- | 9921 | B2B | |||
| 6 | 50QSPI0 | GPIO- | SPI Flash-SCK | ETH0 Reset | 1344 | SDIO0 | JM1- | 9719 | B2B | ||||
| 7 | GPIO | - | USB Reset | Green LED D4 | 45 | SDIO0 | 14 | UART0 | JM1-9217 | B2B | |||
| 8 | 52 | ETH0QSPI0 | - | MDC | 15 | UART0 | JM1-85 | B2BSPI Flash-SCKFB | 5346 | ETH0GPIO | - | MDIO |
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Ethernet |
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On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
Ethernet PHY connection
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Can be routed via PL to any free PL I/O pin in B2B connector.
This LED is connected to PL via level-shifter implemented in
system controller CPLD.
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By default the PHY address is strapped to 0x00, alternate
configuration is possible.
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PHY LED2 INTn Signal. | ||||||||
| 9 | JM1-91 | B2B | 47 | GPIO | - | RTC Interrupt | ||
|---|---|---|---|---|---|---|---|---|
| 10 | JM1-95 | B2B | 48 | I2C1 | - | SCL on-board I2C | ||
| 11 | JM1-93 | B2B | 49 | I2C1 | - | SDA on-board I2C | ||
| 12 | JM1-99 | B2B | 50 | GPIO | - | ETH0 Reset | ||
| 13 | JM1-97 | B2B | 51 | GPIO | - | USB Reset | ||
| 14 | UART0 | JM1-92 | B2B | 52 | ETH0 | - | MDC | |
| 15 | UART0 | JM1-85 | B2B | 53 | ETH0 | - | MDIO |
Gigabit Ethernet
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3.
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an onboard 52MHz oscillator (U15on-board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
USB Ethernet PHY connection
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| PHY Pin | ZYNQ PS | ZYNQ PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | ||
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U15). |
| REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52MHz. |
| RESETB | MIO51 | - | Active low reset. |
| CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
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PLL
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JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
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JTAG Signal
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B2B Connector Pin
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| Note |
|---|
| JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
System Controller I/O Pins
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
...
No hard wired function on PCB, when forced low pulls POR_B low to
emulate power on reset.
...
Active low reset, gated to POR_B.
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| LED0 | - | J3 | Can be routed via PL to any free PL I/O pin in B2B connector. |
| LED1 | - | K8 | Can be routed via PL to any free PL I/O pin in B2B connector. This LED is connected to PL via level-shifter implemented in system controller CPLD. |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY address is strapped to 0x00, alternate configuration is possible. |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | on B2B. |
| MDI | - | - | on B2B. |
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).
USB PHY connection
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U15). |
| REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52MHz. |
| RESETB | MIO51 | - | Active low reset. |
| CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C Address | Notes |
|---|---|---|
| EEPROM | 0x50 | |
| RTC | 0x6F | |
| Battery backed RAM | 0x57 | Integrated into RTC. |
PLL | 0x70 |
Boot Modes
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
MODE Signal State | Boot Mode |
|---|---|
High or open | SD Card |
Low or ground | QSPI |
Boot Modes
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
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MODE Signal State
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High or open
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SD Card
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Low or ground
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QSPI
LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D2 | Green | DONE | Reflects inverted DONE signal, ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted).
On-board Peripherals
Processing System (PS) Peripherals
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Power Rails
Voltages on B2B- Connectors | B2B JM1 - Pin | B2B JM2-Pin | B2B JM3-Pin | Input/ Output | Note |
|---|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8- | Input | supply Supply voltage. | |
| 3.3VIN | 13, 15- | - | Input | supply Supply voltage. | |
| VCCIO13 | 9, 11 | - | - | Input | high High range bank voltage. |
| VCCIO34 | - | 5- | Input | TE0715-xx-15: high range bank voltage,. TE0715-xx-30: high performance bank voltage. | |
| VCCIO35 | - | 7, 9 | - | Input | TE0715-xx-15: high range bank voltage,. TE0715-xx-30: high performance bank voltage. |
| VBAT_IN | 79 | - | - | Input | RTC battery-buffer supply voltage. |
| 3.3V | - | 10, 12 | - | Output | internal Internal 3.3V voltage level. |
| 1.8V | 39 | - | - | Output | internal Internal 1.8V voltage level. |
| DDR_PWR | - | 19- | Output | internal Internal 1.5V or 1.35V voltage level, depends on revision. | |
| VREF_JTAG | 91 | Output | JTAG reference voltage (3.3V). |
Bank Voltages
Bank | Schematic Name | Voltage | TE0715-xx-15 | TE0715-xx-30 |
|---|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | - | - |
| 501 | VCCO_MIO1_501 | 1.8V | - | - |
| 502 | VCCO_DDR_502 | 1.5V | - | - |
| 0 Config | VCCO_0 | 3.3V | - | - |
| 13 HR | VCCO_13 | User | HR: 1.2V to 3.3V | HR: 1.2V to 3.3V |
| 34 HR/HP | VCCO_34 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
| 35 HR/HP | VCCO_35 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
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All dimensions are given in mmmillimeters.
Operating Temperature Ranges
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Hardware Revision History
| Date | Revision | Notes | Link to PCN | Documentation linkLink |
|---|---|---|---|---|
| 2016-06-21 | 04 | Second production release | Click to see PCN | TE0715-04 |
| - | 03 | First production release | TE0715-03 | |
| - | 02 | Prototypes | TE0715-02 | |
| - | 01 | Prototypes |
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-01-25 | Jan Kumann | New block diagram. | |
| 2017-01-14 | V50 | Jan Kumann | Product revision 04 images added. Formatting changes and small corrections. |
| 2016-11-15 | V45 | Thorsten Trenz | Added B2B Connector section. |
| 2016-10-18 | V40 | Ali Naseri | Added table "power rails". |
| 2016-06-28 | V38
| Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pin-out Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. |
| 2016-04-27 | V33 | Thorsten Trenz, Emmanuel Vassilakis | Added table "Recommended Operating Conditions". Storage Temperature edited. |
| 2016-03-31 | V10 | Philipp Bernhardt, Antti Lukats | Initial version. |
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