Page History
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Storage device name | Content | Notes | |
|---|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. | |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. | |
SPI Flash Quad Enable bit | Programmed | - | |
SPI Flash main array | Demo design | - | |
eFUSE USER | Not programmed | - | |
eFUSE Security | Not programmed | - | |
| Si5338 OTP NVM | Not programmed | Default settings pre programmedCan be pre-programmed for special order only |
Signals, Interfaces and Pins
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| I/O | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A125MHz | - | Bank 34 clock input, default disabled, User clock. |
CLK3B | - | Not used, disabled. |
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Overview
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