Page History

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1. 6-pin header J26 for selecting Bank34 VCCIO voltage
2. 6-pin header J27 for selecting XMOD/JTAG reference voltage
3. Samtec Razor Beam™ LSHM-150 B2B connector JM1
4. Samtec Razor Beam™ LSHM-150 B2B connector JM2
5. JTAG/UART header JX1 ('XMOD FTDI JTAG Adapter' compatible pin-assignment)
6. Ultra small SMT coaxial connector J5
7. Ultra small SMT coaxial connector J6
8. Ultra small SMT coaxial connector J7
9. Ultra small SMT coaxial connector J8
10. User LED D1 (green)
11. User LED D2 (red)
12. LED D3 (red) indicating 'Programming DONE'-signal from module's FPGA
13. SFP+ Connector J1
14. 10-pin header soldering-pads J4 for access to SoM's PL IO-banks (LVDS-pairs possible, VCCIO voltages: 3.3V, 3.3V_OUT from module)
15. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter' compatible pin-assignment) with 4 additional pins for reference-clock input to 4 x 5 cm SoM and differential one LVDS-pair for ADCanalog signal input
16. 50-pin header soldering-pads J20 for access to SoM's PL IO-banks (LVDS-pairs possible, VCCIO voltages: 3.3V, Bank34 VCCIO voltage)
17. 50-pin header soldering-pads J17 for access to SoM's PL IO-banks (LVDS-pairs possible, VCCIO voltages: 3.3V, V_CFG from module)

Key Features

• SFP+ connector (Enhanced small form-factor pluggable), supports data transmission rates up to 10 Gbit/s
• 4 Hirose Ultra small SMT coaxial connectors, supports data transmission rates up to 6 Gbit/s
• TE 4 x 5 cm SoM programable by JTAG header (JX1)
• 2 x user LEDs routed to IO-pins of the SoM
• Soldering-pads J17 and J20 as place-holder for further possibilities to access to SoMs IO-bank-pins, usable as LVDS-pairs
• Soldering-pads J3 and J4 as place-holder for access to JTAG- or IO-ports of the SoM
  

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Table 1: SFP+ connector pin-assignment

Ultra small SMT coaxial connector

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JTAG/UART Interface

The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment:

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Further two additional pins (13, 14) are designated as LVDS-pair for analog signals and routed to the ADC-unit of the SoM. This LVDS-pair is fused with has 1K serial resistors on both conductors and has on the B2B-connector JM1 the pins JMJM1-25 and JMJM1-27 with the net-names 'ADC_P' and 'ADC_N'.

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There are two LEDs D1 (green) and D2 (red) available to the user. The green LED D1 is connected to the pin MIO9 (JB1-92)B2B-connector pin JM2-26 with the net-name 'GLED', the red LED D2 is connected to the pin JB3JM2-90 24 with the net name 'RLED'.

LED D3 (red) is linked to the SoM's output signal 'DONE' indicating that the FPGA-modul is programmed properly.

Header place-holder J4

The place-holder J4 with solder-pads to mount a 2-row 10-pin header provides the capability, to access via this header the SDIO-port of the mounted 4 x 5 SoM, if available. For this purpose, there is also voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary due to the different voltage levels of the Micro SD Card (3.3V) and MIO bank of the Xilinx Zynq-chip (1.8V)additional 3 LVDS-pairs with the pin-mapping 3-4, 7-8 and 9-10. The LVDS-pairs are operable with the VCCIOs 3.3V or 3.3V_OUT from mounted module.

Header place-holder J17 and J20

The place-holders J17 and J20 with solder-pads to mount 2-row 50-pin headers provide the capability to access the PL IO-bank pins of the mounted 4 x 5 SoM.

With mounted header J17 J20 there are 42 IO's of PL-IO-bank 13 34 of the 4 x 5 SoM available (B2B-connector JB3), which are also usable as 21 LVDS-pairs. On this header the IO's are operable with fixed ( 3.3V ) or selectable VCCIO-voltage VCCIODVCCIO34. 

On header J20 J17 there are 42 36 IO's available of PL-IO-bank 35 (B2B-connector JB1)14. This IO's are also usable as 21 18 LVDS-pairs and operable with fixed 3.3V or module's config-VCCIO V_CFG (depending on module's configuration: 3.3V ) or selectable VCCIO-voltage VCCIOAor 1.8V). This header provides also a QSPI interface consisting of 6 IO's.

Power

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

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Figure 3: Power-On sequence diagram

Configuring VCCIO 

On the TEBA0841 TEBB0714 carrier board different VCCIO configurations can be chosen by the jumper J26 and J27.

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Summary of VCCIO-configuration

On the TEBA0841 TEBB0714 carrier board the PL IO-bank's supply voltages of the 4x5 SoM (VCCIOA, VCCIOD; see 4x5 Module Integration Guide) are connected to the base-board VCCIO-voltage VCCIOA and VCCIOD, which are selectable between the supply-voltages 1.8V, 2.5V and 3.3V via jumper J26 and J27.

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