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On both interfaces (JX1, J3), the pins with the net-names B14_L25 and B14_L0 are available as user IO's which could be used as UART-interface for example.
LEDs
There are two LEDs D1 (green) and D2 (red) available to the user. The green LED D1 is connected to the B2B-connector pin JM2-26 with the net-name 'GLED', the red LED D2 is connected to the pin JM2-24 with the net name 'RLED'.
LED D3 (red) is linked to the SoM's output signal 'DONE' indicating that the FPGA-modul is programmed properly.
Header place-holder J4
The place-holder J4 with solder-pads to mount a 2-row 10-pin header provides additional 3 LVDS-pairs with the pin-mapping 3-4, 7-8 and 9-10. The LVDS-pairs are operable with the VCCIOs 3.3V or 3.3V_OUT from mounted module.
Header place-holder J17 and J20
Three LEDs are present on the TEBB0714 base-board with following functionality:
| LED designator | color | pin net-name | B2B-connector | indicating |
|---|---|---|---|---|
| D1 | green | GLED | JM2-26 | available to user |
| D2 | red | RLED | JM2-24 | available to user |
| D3 | red | DONE | JM1-96 | FPGA-modul programmed properly |
Table 4: LED's funtionality
Place holders for optional pin-headers
The TEBB0714 base-board has place-holders The place-holders J17 and J20 with solder-pads to mount 2-row 50-pin headers provide the capability optional pin-headers capable to access the PL IO-bank pins of the mounted 4 x 5 SoM. With mounted header J20 there are 42 pin-headers SoM's IO's of PL-IO-bank 34 of the 4 x 5 SoM available, which are available to the user, a large quantity of these IO's are also usable as 21 as LVDS-pairs. On this header This pin-headers provide also VCCIO voltages to operate the IO's are operable with fixed 3.3V or selectable VCCIO-voltage VCCIO34.On header J17 there are 36 IO's available of PL-IO-bank 14. This IO's are also usable as 18 LVDS-pairs and operable with fixed 3.3V or module's config-VCCIO properly.
Following table gives a summary of the optional pin-headers of the base-board:
Connector designator | pin-header layout | # IO's | # LVDS-pairs | available VCCIOs | interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 3 | 3.3V 3.3V_OUT from mounted module | - |
| J17 | 2-row 50-pin | 42 (Bank 14) | 18 | 3.3V V_CFG (depending on module's configuration: 3.3V or 1.8V) | QSPI (6 IO's allocated) |
| J20 | 2-row 50-pin | 42 (Bank 34) | 21 | 3.3V selectable VCCIO34 (1.8V, 2.5V, 3.3V_OUT) | - |
| J3 | 2-row 16-pin | 12 | 2 | 3.3V V_CFG (depending on module's configuration: 3.3V or 1.8V) | JTAG (4 IO's allocated) UART (2 IO's allocated) ADC (1 LVDS-pair) Reference MGT-CLK0 (1 LVDS-pair) |
Table 5: Summary of optional pin-headers. This header provides also a QSPI interface consisting of 6 IO's.
Power
Power Supply
Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.
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| Connector | 3.3V pin | GND pin |
|---|---|---|
| JX1 | JX1-5, JX1-6, | JX1-1, JX1-2 |
| J3 | J3-5 | J3-1, J3-2 |
| J4 | J4-5 | J4-1, J4-2 |
| J20 | J20-5, J20-46 | J20-1 , J20-2 , J20-49 , J20-50 |
| J17 | J17-5, J17-46 | J17-1 , J17-2 , J17-49 , J17-50 |
Table 46: Connector-pins capable for external 3.3V power-supply
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