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Connector designator | pin-header layout | # IO's | # LVDS-pairs | available VCCIOs | interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 3 | 3.3V 3.3V_OUT from mounted module | - |
| J17 | 2-row 50-pin | 42 (Bank 14) | 18 | 3.3V V_CFG (depending on module's configuration: 3.3V or 1.8V) | QSPI (6 IO's allocated) |
| J20 | 2-row 50-pin | 42 (Bank 34) | 21 | 3.3V selectable VCCIO34 (1.8V, 2.5V, 3.3V_OUT) | - |
| J3 | 2-row 16-pin | 12 | 2 | 3.3V V_CFG (depending on internal module's configurationVCCIO: 3.3V or 1.8V, depending on configuration) | JTAG (4 IO's allocated) UART (2 IO's allocated) ADC (1 LVDS-pair) Reference clock input MGT-CLK0 (1 LVDS-pair) |
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Following table describes how to configure the base-board supply-voltage VCCIO34 by jumper J26:
base-board |
|---|
supply-voltage VCCIO34 |
|---|
| Jumper J26 | |
|---|---|
| 1.8V | J26:1-2 |
| 2.5V | J26:3-4 |
| 3.3V | J26: 5-6 |
Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on. Other pins are left open.
By jumper J27 the (depending on module's configuration: 3.3V or 1.8V)reference voltage of the JTAG/UART header JX1 (pin 6 VIO) can be selected:
Reference VCCIO |
|---|
JTAG |
|---|
/UART Header V_CFG | Jumper J27 |
|---|---|
| 1.8V | J27:1-2 |
| V_CGF0 (internal module's VCCIO: 3.3V or 1.8V, depending on configuration) | J27:3-4 |
| 3.3V_OUT | J27: 5-6 |
Table 7: Configuration of reference VCCIO JTAG/UART header.
Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on. Other pins are left open.
| Note |
|---|
| It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4x5 module to avoid failures and damages to the functionality of the mounted SoM. |
Technical Specifications
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