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  1. 6-pin header J26 for selecting Bank34 VCCIO voltage
  2. 6-pin header J27 for selecting XMOD/JTAG reference voltage
  3. Samtec Razor Beam™ LSHM-150 B2B connector JM1
  4. Samtec Razor Beam™ LSHM-150 B2B connector JM2
  5. JTAG/UART header JX1 ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  6. Ultra small SMT coaxial connector J5
  7. Ultra small SMT coaxial connector J6
  8. Ultra small SMT coaxial connector J7
  9. Ultra small SMT coaxial connector J8
  10. User LED D1 (green)
  11. User LED D2 (red)
  12. LED D3 (red) indicating 'Programming DONE'-signal from module's FPGA
  13. SFP+ Connector J1
  14. 10-pin header soldering-pads J4 for access to SoM's PL IO-banks (LVDS-pairs possible)
  15. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter' compatible pin-assignment) with 4 additional pins for reference-clock input to 4 x 5 cm SoM and one LVDS-pair for analog signal input
  16. 50-pin header soldering-pads J20 for access to SoM's PL IO-banks (LVDS-pairs possible)
  17. 50-pin header soldering-pads J17 for access to SoM's PL IO-banks (LVDS-pairs possible)

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The JTAG-interface of the mounted 4 x 5 SoM can be accessed via the headers JX1 or J3 with 4 additional pins for reference-clock input to 4 x 5 cm SoM and one LVDS-pair for analog signal input.

This headers have header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment:

JX1 pinJX1 pin net-nameB2B J3 pinJX1 pin net-nameB2B
C (pin 4)TCKJM1-90 4TCKJM1-90
D (pin 8)TDOJM1-88 8TDOJM1-88
F (pin 10)TDIJM1-86 10TDIJM1-86
H (pin 12)TMSJM1-92 12TMSJM1-92
A (pin 3)B14_L25JM2-97 3B14_L25JM2-97
B (pin 7)B14_L0JM2-99 7B14_L0JM2-99
E (pin 9)BOOTMODEJM2-100 9BOOTMODEJM2-100
G (pin 11)PROG_B
JM2
JM1-94

Table 3: JTAG header JX1 pin-assignment

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 11PROG_BJM1-94
--- 13XADC_PJM1-25 (ADC_P, decoupling capacitator 100 nF)
--- 14XADC_NJM1-27 (ADC_N, decoupling capacitator 100 nF)
--- 15CLK0_PJM1-2 (MGT_CLK0_P, 1KΩ serial resistor)

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--- 16CLK0_NJM1-4 (MGT_CLK0_N, 1KΩ serial resistor)

Table 3: JTAG/UART header JX1 / J3 pin-assignmentFurther two additional pins (13, 14) are designated as LVDS-pair for analog signals and routed to the ADC-unit of the SoM. This LVDS-pair has 1K serial resistors on both conductors and has on the B2B-connector JM1 the pins JM1-25 and JM1-27 with the net-names 'ADC_P' and 'ADC_N'.

On both interfaces (JX1, J3), the pins with the net-names B14_L25 and B14_L0 are available as user IO's which could be used as UART-interface for example.

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Note
It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4x5 module to avoid failures and damages to the functionality of the mounted SoM.

 

Technical Specifications

Absolute Maximum Ratings

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